The RISC-V Summit North America, held on 22-23 October 2025 in Santa Clara, California, showcased the most recent CPU cores that includes new vector processors, high-speed interfaces, and peripheral subsystems. These CPU cores have been accompanied by reference boards, software program design kits (SDKs), and toolchains.
The present additionally supplied a sneak peek of the RISC-V’s design ecosystem, which is maturing quick with the RVA23 software profile and RISC-V Software program Ecosystem (RISE), a Linux Basis mission. The rising ecosystem encompasses compilers, system libraries, language runtimes, simulators, emulators, system firmware, and extra.
“The efficiency hole between high-end Arm and RISC-V CPU cores is narrowing and a close to parity is projected by the top of 2026,” mentioned Richard Wawrzyniak, principal analyst for ASIC, SoC and IP at The SHD Group. He named Andes, MIPS, Nuclei Techniques, and SiFive as market leaders in RISC-V IP. Wawrzyniak additionally talked about new entrants similar to Akeana, Tenstorrent, and Ventana.
Andes, boasting 20 years of experience within the semiconductor IP enterprise, was a outstanding presence within the corridors of the RISC-V Summit in Santa Clara. It’s a founding member of RISC-V Worldwide and a pure-play IP vendor. On the RISC-V Summit, Andes displayed its processor lineup, together with AX45, AX46, AX66, and Cuzco.
Determine 1 The processor lineup was showcased on the RISC-V Summit in Santa Clara. Supply: Andes
Andes claims that these RISC-V processors, that includes highly effective compute and environment friendly management, present the architectural variety required in synthetic intelligence (AI) functions. AX45 and AX46 processors have been taped out and are delivery in volumes. Right here, Andes additionally gives in-chip firmware, tester software program, on-board software program, and on-cloud software program as a part of its {hardware} IP monitoring choices.
Although RISC-V is having fun with a strong deployment in automotive, Web of Issues (IoT), and networking, AI was all the fashion on the RISC-V Summit ground. “If RISC-V has a tailwind, it’s AI,” Wawrzyniak mentioned.
RISC-V world’s AI second
Andes claims it’s driving RISC-V into the AI world with options similar to superior vector processing. And that its RISC-V processors are powering gadgets from the battery-sipping edge to high-performance knowledge facilities. Andes additionally claims that 38% of its income comes from AI designs.
Corporations like Andes may also convey differentiation and effectivity to AI processor designs by automated customized extensions. “We’re getting there, and the deployment velocity is spectacular,” mentioned Dr. Charlie Su, president and CTO of Andes Expertise.
Determine 2 Meta deployed two generations of AI accelerators for coaching and inference utilizing RISC-V vector/scalar cores. Supply: Andes
“RISC-V is getting higher for AI functions in knowledge facilities,” mentioned Ty Garibay, president of Condor Computing. “RVA23 has an enormous funding in options for knowledge center-class AI designs.” Condor Computing, an entirely owned subsidiary of Andes, based in 2023, develops high-performance RISC-V IPs and is predicated in Austin, Texas.
Wawrzyniak of SHD Group acknowledges that AI functions are driving the adoption of RISC-V-enabled system-on-chips (SoCs). “The heterogeneous nature of SoCs has created alternatives for a number of CPU architectures,” he mentioned. “These SoCs can assist each RISC-V and different ISAs, permitting functions to select one of the best core for every operate.”
Furthermore, the various wants for AI acceleration are fueling the demand for RISC-V. “RISC-V CPU IP distributors can extra simply introduce new and extra highly effective CPU cores, which extends the attain of RISC-V into AI functions that require higher compute energy,” Wawrzyniak mentioned.
Throughout his keynote, Wawrzyniak mentioned that preliminary RISC-V deployments have been pushed by embedded functions similar to networking, sensible sensors, storage, and wearables. “RISC-V is now transitioning to higher-end functions like ADAS and knowledge facilities as AI expands to these functions.”
RISC-V processor duo
On the RISC-V Summit, Andes supplied extra particulars about its new software processors. It showcased AX66, a mid-range software processor, and Cuzco, a high-end software processor; each are RVA23-compliant. AX66—incorporating as much as 8 cores—options twin vector pipes with VLEN=128 and front-end decode 4-wide. It has a shared L3 cache of as much as 32 MB.
Determine 3 AX66 is a 64-bit multicore CPU IP for creating a high-performance quad-decode 13-stage superscalar out-of-order processor. Supply: Andes
On the upper finish, Cuzco options time-based scheduling with a time useful resource matrix to find out instruction problem cycles after decoding, thereby decreasing logic complexity and dynamic energy for vast machines. Cuzco’s decode is both 6-wide or 8-wide, and it has 8 execution pipelines (2 per slice).
Cuzco incorporates as much as 8 cores and affords a shared L3 cache of as much as 256 MB. The Cuzco RISC-V processor has been applied at 5-nm nodes with 8 execution pipelines and seven million gates. It options an L2 configuration with 2MB and is focused for a 2.5-GHz velocity.
Determine 4 The Cuzco design represents the primary in a brand new class of RISC-V CPUs geared toward knowledge center-class efficiency whereas sustaining energy effectivity and space advantages. Supply: Andes
For the event of those RISC-V processors, the AndeSight built-in improvement surroundings (IDE) helps design engineers generate recordsdata for LLVM to acknowledge new directions. Then there may be AndesAIRE software program, which facilitates graph-level optimization for pruning and quantization in addition to back-end-aware optimization for fusion and allocation.
For OS assist, the processors adjust to RVA22 and RVA23 profiles and SoC {hardware} and software program platforms. Andes additionally gives further assist to make sure that the Linux kernel is upstream-compatible.
Cuzco, unveiled at Sizzling Chips 2025 earlier this yr, encompasses a time-based out-of-order microarchitecture engineered to ship excessive efficiency and effectivity throughout compute-intensive functions in AI, knowledge middle, networking, and automotive markets. Andes supplied a preview of this out-of-order CPU on the RISC-V Summit.
Condor Computing developed the Cuzco RISC-V core, which is absolutely built-in into the Andes toolchain and ecosystem. Condor lately accomplished full {hardware} emulation of its new CPU IP whereas efficiently booting Linux and different working techniques.
“Condor’s microarchitecture combines superior out-of-order execution with novel {hardware} methods to dramatically enhance performance-per-watt and silicon effectivity,” Andes CTO Su mentioned. “It’s ideally fitted to demanding CPU workloads in AI, automotive compute, functions processing, and past.”
The primary buyer availability of the Cuzco RISC-V processor is predicted within the fourth quarter of 2025.
The RISC-V adoption
Based on Wawrzyniak, chip designers are actually each Arm and RISC-V processor architectures. “The RISC-V ISA and its rising ecosystem have interjected competitors as soon as once more into the SoC design panorama.”
Moreover, the customized RISC-V ISA extensions empower innovation and tailor-made efficiency. Not surprisingly, due to this fact, the adoption of RISC-V by giant expertise corporations similar to Broadcom, Google, Meta, MediaTek, Qualcomm, Renesas, and Samsung continues to validate the utility of the RISC-V ISA within the semiconductor business.
RISC-V, as soon as an instructional train, has come a great distance since its launch in Might 2010 on the College of California, Berkley. Nonetheless, as Krste Asanovic, chief architect at SiFive, mentioned throughout his keynote, RISC-V will proceed to evolve throughout completely different verticals and that it’ll be round for a very long time.
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