The analog-based timing semiconductor world, comprising crystals and phase-lock loops (PLLs), is going through a conundrum. Whereas crystals present increased efficiency at decrease frequencies, PLLs accommodate increased frequencies with decrease efficiency. An Irvine, California-based timing startup claims to have a solution to this conundrum. It digitally synthesizes timing indicators utilizing CMOS expertise, thereby changing legacy analog chains.
Learn the full story at EDN’s sister publication, Planet Analog.
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