HomeElectronicsSuperior Packaging Improve MOSFET Effectivity

Superior Packaging Improve MOSFET Effectivity


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New energy MOSFETs with optimized thermal and electrical design ship decrease losses, increased effectivity, and improved reliability for industrial energy programs.

Superior Packaging Improve MOSFET Effectivity
Superior Packaging Improve MOSFET Effectivity

Toshiba has unveiled two high-performance N-channel energy MOSFETs—TPM1R908QM (80 V) and TPM7R10CQ5 (150 V)—constructed on its newest SOP Advance(E) packaging platform. Geared toward industrial switched-mode energy provides, information facilities, and telecom infrastructure, the units promise decrease conduction losses, improved thermal dealing with, and better switching effectivity in compact footprints.

It has SOP Advance(E) design, which addresses efficiency bottlenecks attributable to electrical and thermal parasitics in conventional MOSFET packages. By minimizing lead inductance and optimizing inside thermal paths, the brand new package deal achieves 65% decrease package deal resistance and 15% decrease thermal resistance in comparison with its predecessor, SOP Advance(N). The end result: decreased vitality waste, cooler operation, and better reliability underneath excessive load.

The important thing options are:

  • Typical RDS(on) 1.5 mΩ (max. 1.9 mΩ) and 5.7 mΩ (max. 7.1 mΩ)  at VGS = 10 V
  • Drain present as much as 238 A and 120 A at 25 °C case temperature
  • Low gate-switching cost (35 nC) and  (43 nC)  and output cost (111 nC) for decreased switching losses
  • Quick switching with rise time of fifty ns, fall time of 38 ns
  • Thermal resistance channel-to-case: 0.6 °C/W

Each MOSFETs share the identical compact 4.9 mm × 6.1 mm SOP Advance(E) footprint, enabling space-constrained designs with out sacrificing current-handling functionality. The improved thermal path permits operation as much as 175 °C channel temperature, extending system longevity and sustaining effectivity underneath steady excessive load.

Designers can speed up improvement utilizing Toshiba’s G0 and G2 SPICE fashions for correct circuit simulation and efficiency prediction.By combining superior semiconductor traits with a thermally and electrically optimized package deal.

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