RISC-V pioneer SiFive has introduced the second era of its “intelligence” household, designed for on-device machine studying and synthetic intelligence (ML and AI) on the edge: the X160 Gen. 2 and X180 Gen. 2, plus upgraded X280, X390, and XM Gen. 2 designs.
“AI is catalyzing the following period of the RISC-V revolution,” claims SiFive chief government officer Patrick Little on the occasion of the corporate’s newest launches. “We’re seeing sturdy traction together with adoption of the brand new X100 collection by two Tier 1 U.S. semiconductor firms. Our new 2nd Technology Intelligence IP builds on this momentum, including new options and configurability to speed up our clients’ designs and time to market.”
The corporate’s newest launches, which take the type of proprietary IP constructed atop the free and open supply RISC-V instruction set structure, come a 12 months after the discharge of the Intelligence XM Sequence — usable, the corporate mentioned on the time, as an accelerator for on-device synthetic intelligence workloads, but in addition configurable as the one CPU in a system “incorporating no host CPU.”
The second-generation Intelligence household consists of an upgraded XM Sequence Gen. 2, although on the time of writing SiFive had not publicly disclosed full specs past the promise of 16 tera-operations per second (TOPS) of INT8 compute per cluster and an structure “now closely tuned for LLMs [Large Language Models].” It has, nevertheless, launched particulars concerning its upgraded X280 and X390 Gen. 2 IP, in addition to new entry-level designs dubbed the X160 and X180 Gen. 2. These are 32-bit RV32I(E) and 64-bit RV64I implementations designed for energy-efficient edge AI on the Web of Issues (IoT) and supporting as much as 4 cores per cluster, having no reminiscence administration unit, and with 128-bit vector size help.
The second era consists of two all-new IPs: the X160 and X180 Gen. 2, concentrating on the Web of Issues (IoT). (📷: SiFive)
The X280 Gen. 2 sits above these with an RVA23-compliant RISC-V implementation, help for one, two, or 4 cores per cluster, an SV48 reminiscence administration unit, 512-bit vector size help. Lastly, the X390 Gen. 2 provides SV57 MMU capabilities and 1024-bit vector size help. All the brand new fashions embody SiFive Scalar Coprocessor Interface (SSCI) and Vector Coprocessor Interface Extension (VCIX) accelerator management interfaces, and embody a loosely-coupled vector pipeline the corporate claims will keep away from reminiscence stalls.
All IP is accessible to license now, SiFive has confirmed, although with pricing not publicly disclosed, with the primary silicon anticipated within the second quarter of 2026. Extra info is accessible on the SiFive web site.
