The world we live in is more and more turning into software-defined, the place synthetic intelligence (AI) is including the following layer of performance. And it’s driving the necessity for extra compute to allow the software-enabled performance. Nonetheless, with this large development in compute content material, Moore’s Legislation scaling might be inadequate to assist the variety of transistors for the wanted compute.
Enter 3D ICs, disaggregating the performance of silicon right into a set of chiplets after which heterogeneously integrating them on a sophisticated integration platform. “Hyperscalers, driving the compute envelope, are significantly pushing the acute the place 3D ICs are wanted,” stated Michael White, VP of Calibre Design Options at Siemens EDA.
White additionally famous automotive designs the place self-driving know-how content material is driving the necessity for 3D ICs. On the Design Automation Convention (DAC) held in San Francisco, California, on 22-25 June 2025, Siemens EDA introduced two key additions to its EDA portfolio to deal with and overcome the complexity challenges related to the design and manufacture of two.5D and 3D IC units.
First, the corporate’s Innovator3D IC suite allows chip designers to effectively writer, simulate, and handle heterogeneously built-in 2.5D and 3D IC designs. Second, its Calibre 3DStress software program leverages superior thermo-mechanical evaluation to establish {the electrical} affect of stress on the transistor stage.
Determine 1 The brand new instruments purpose to dramatically cut back threat and improve the design, yield, and reliability of advanced, next-generation 2.5D/3D IC designs. Supply: Siemens EDA
“These options assist designers obtain the wanted compute efficiency whereas rising yield and reliability and lowering value,” White added. “Additionally they provide the flexibility to leverage greater bandwidth between the chiplets positioned on an interposer.” He calls this an inflection level within the design course of and instruments wanted for the design flows.
Chiplet integration with Innovator3D IC
Keith Felton, principal technical product supervisor for 3D IC options at Siemens EDA, expanded on 3D IC being an inflection level, marking a transition from single design-centric method to system-centric method. “It impacts design flows and instruments, necessitating a system-centric method from early planning by way of remaining sign-off in 4 methods,” he added.
First, chip designers want system flooring planning to optimize energy, efficiency, space, and reliability throughout silicon, package deal, interposer, and even PCB. Second, they need to begin utilizing multi-physics modeling to simulate advanced thermo-mechanical interactions that affect electrical and structural efficiency.
Third, IC designers have to have a technique for scalability to handle and talk heterogeneous information throughout enterprise-wide groups and keep digital continuity as a result of there are a whole lot of silicon designs encompassing chiplets. Fourth, designers should have a technique for multi-die sign-off, enabling 3D verification of connectivity, interfaces, interconnect reliability, and electrostatic discharge (ESD) resiliency.
So, Innovator3D IC suite gives a quick, predictable path for planning and heterogeneous integration, substrate/interposer implementation, interface protocol evaluation compliance and information administration of designs, and design information IP.
Determine 2 Innovator3D IC suite facilitates design, verification, and information administration of two.5D and 3D IC chiplets. Supply: Siemens EDA
Innovator3D IC—comprising 4 constructing blocks—provides an AI-infused consumer expertise with intensive multithreading and multicore capabilities to realize optimum capability and efficiency on 5+ million pin designs. First, Innovator3D IC Integrator comes with a consolidated cockpit for establishing a digital twin, utilizing a unified information mannequin for design planning, prototyping, and predictive evaluation.
Second, Innovator3D IC Format facilitates correct-by-construction package deal interposer and substrate implementation. Third, Innovator3D IC Protocol Analyzer can be utilized for chiplet-to-chiplet and die-to-die interface compliance evaluation. It’ll be important in making certain compliance with protocols similar to Common Chiplet Interconnect Categorical (UCIe). Lastly, the Innovator3D IC Information Administration half is focused on the work-in-progress administration of designs and design information IP.
“Innovator3D IC is focusing on the optimization of two.5 and 3D IC design efficiency to eradicate late-stage modifications by enabling early prototyping and planning,” Felton stated. “It accelerates compliance with protocols for chiplet integration and gives a core workflow that design groups want for 3D IC chiplet integration.”
Calibre 3DStress for package deal verification
Calibre 3DStress—the second a part of Siemens EDA’s resolution to streamline the design and evaluation of advanced, heterogeneously built-in 3D ICs—helps correct, transistor-level evaluation, verification, and debugging of thermo-mechanical stresses and warpage within the context of 3D IC packaging.
It allows IC designers to evaluate how chip-package interplay will affect the performance of their designs earlier within the improvement cycle. Shetha Nolke, principal product supervisor for Calibre 3DStress at Siemens EDA, instructed EDN that this device performs three key duties for chip-package stress evaluation in 3D IC designs.
First, stress simulation ensures correct die ranges below thermal and mechanical circumstances. Second, what-if evaluation optimizes IP, cell, or chip placement throughout early design levels. Third, it performs stress-aware circuit evaluation utilizing again annotation of gadget stress to reduce electrical affect.
Determine 3 With the thinner dies and better package deal processing temperatures of two.5D/3D IC architectures, designers usually found that designs validated and examined on the die stage now not conform to specs after packaging reflows. Supply: Siemens EDA
3D ICs more and more face stress- and warpage-related packaging challenges. That features thermal challenges similar to non-uniform warmth technology and dissipation, which can lead to greater temperatures and temperature gradients. Then, there are thermo-mechanical points, the place packaging course of levels expertise excessive temperature and stuck constraints.
Lastly, thinned dies and ultra-low-k dielectrics enhance mechanical stress-induced issues. “As a number of chiplets are built-in right into a package deal, they expertise thermal impacts as a result of warmth isn’t in a position to escape readily,” Nolke stated. “Whereas mechanical elements are coming from incorporating package deal parts, Calibre 3DStress can mannequin it earlier than fabrication.”
Calibre 3DStress delivers correct die-level stress simulation utilizing finite factor evaluation at a nano-meter characteristic scale. It additionally gives visualization of stress and warpage outcomes whereas facilitating electrical and mechanical verification.
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