“Info are cussed issues” (John Adams, et al).
I added two 50-ohm outputs to the schematic of my revealed voltage-to-frequency converter (VFC) circuit (Determine 1). Then, I designed a PCB, bought the (largely) surface-mount elements, loaded and re-flow soldered them onto the PCB, after which examined the design.
Determine 1 VFC design that operates from 100 kHz to past 100 MHz with a single 5.25-V provide, offering sq. wave outputs at 1/2 and 1/4 the primary oscillator frequency.
The {hardware} implementation of the circuit may be seen in Determine 2.
Determine 2 The {hardware} implementation of the 100MHz VFC was created in an effort to root out the info that may solely be obtained after it was constructed.
My goal was to get the info concerning the operation of the circuit.
Principle and simulation are essential, however the info are identified solely after the circuit is constructed and examined. That’s when the unintended/sudden penalties are seen.
The circuit largely carried out as anticipated, however there have been some important points that needed to be addressed in an effort to get the circuit performing effectively.
Sensitivity of the v-to-f
My first concern was the excessive sensitivity of the circuit to minute modifications within the enter voltage. The sensitivity is 100 MHz per 5 volts, i.e., 20 MHz per volt. Meaning a 1-mV change on the enter ends in a 20-kHz change within the output frequency!
So, how do you provide an enter voltage that’s virtually completely devoid of noise and/or ripple, which can trigger jitter on the oscillator sign? To take care of this drawback, I used a battery provide, 4 alkaline batteries in sequence, linked to a 10-turn, 100-kΩ potentiometer to drive the enter of the circuit with about 0 to six V. This labored fairly effectively. I added a ten kΩ resistor in sequence with the non-inverting enter of U1 for cover in opposition to overvoltage.
Issues and fixes
The primary sudden drawback was that the NE555 timer didn’t present ample drive to the voltage inverter circuit and the voltage doubler circuit. This one is on me; I didn’t look fastidiously on the datasheet, which says it may well provide numerous output present, however at excessive present, the output voltage drops a lot that the inverter and the doubler circuits don’t present sufficient output voltage. And the LTspice mannequin I used for simulation was a really unrealistic mannequin. I like to recommend that it not be used!
I mounted this through the use of a 74HC14 Schmitt set off chip to interchange the NE555 timer chip. The 74HC14 supplies loads of present and voltage to drive the 2 circuits. I carried out the 74HC14 circuitry as an outboard attachment to the primary PCB.
I modified the output of the voltage doubler circuit to a regulated 6 V (R16 modified to 274 Ω and R18 to three.74 kΩ, and D8, D9 modified to SD103). This permits U1 to function with an enter voltage of as much as about 5.9 V. Additionally, I substituted a TLV9162 twin op-amp for U1/U2 as a result of the price of the TLV9162 is far lower than that of the LT1797.
With the proper voltages provided to U1/U2, I started testing the circuit, and I discovered that the oscillator would grasp at a frequency of about 2 MHz. This was attributable to the paralleled Schmitt set off inverters. One inverter would change earlier than the opposite one, which might then sink the present from the inverter that had switched to the HIGH output state, and the oscillator would cease functioning. Paralleling inverters, that are pushed by a comparatively slowly falling (or rising) enter sign, is unquestionably not a viable thought!
To repair the issue, I eliminated U4 from the circuit and put a 22-Ω resistor in sequence with the output of inverter U3 to reduce the present load on it, and the oscillator operated as anticipated.
I made some modifications to the current-to-voltage converter circuit to offer extra adjustment vary and to make use of the optimum values for the 5-V provide. I modified R8 to three.09 kΩ, potentiometer R9 to 1 kΩ, and R13 to 2.5 kΩ.
Changes
There are two changes supplied: R9 is an adjustment for the current-to-voltage converter U2, and R11 is an offset present adjustment.
I adjusted R9 to set the oscillator frequency to 100 MHz with the enter voltage set to five.00 V, after which adjusted R11 at 2 MHz.
The p.c error of the circuit will increase on the decrease frequencies; presumably because of diode leakage currents, or nonlinear conduct of the frequency to voltage converter consisting of D2 – D4 and C8 – C11?
Take a look at outcomes
With the famous modifications carried out, I started testing the VFC. The issue of jitter on the output sign was obvious, particularly on the decrease frequencies.
I noticed that ripple and noise on the 5-V provide would trigger jitter on the output sign. As famous on the schematic, the oscillator frequency is a perform of the provision voltage.
To keep away from this drawback, I as soon as once more opted to make use of batteries to offer the provision voltage. I used six alkaline batteries to produce about +9 V and controlled the voltage all the way down to +5 V with an LM317T regulator and some different elements.
This setup achieves concerning the minimal ripple and noise on the provision and the minimal oscillator jitter. The remaining potential sources of noise/jitter are the switching provides for U1, the suggestions voltage to U1, and the switching on and off of the counters and the inverters, which might trigger noise on the +5-V provide.
The frequency versus enter voltage plot just isn’t as linear as anticipated, however it’s fairly good over a variety of enter voltage from 50 mV to five.00 V for a corresponding frequency vary of 1.07 MHz to 103.0 MHz (Determine 3 and Determine 4). The p.c error versus frequency is proven in Determine 5.
Determine 3 The frequency from 1.07 MHz to 103.0 MHz versus enter voltage from 50 mV to five.00 V.
Determine 4 The frequency (as much as 2 MHz) versus enter voltage when Vin < 0.1 V.
Determine 5 The p.c error versus frequency.
Waveforms
Some waveforms are proven in Determine 6, Determine 7, Determine 8, and Determine 9. Most are from the divide-by-2 output as a result of it’s extra visually fascinating than the three.4-ns output from the oscillator (multiply the divide-by-2 frequency by 2 to get the oscillator frequency).
The enter voltage ranges from 10 mV to five V to supply the 200 kHz to 100 MHz oscillator/inverter output.
Determine 6 Oscilloscope waveform with a divide-by-two output at 100 kHz.
Determine 7 Oscilloscope waveform with a divide-by-two output at 500 kHz.
Determine 8 Oscilloscope waveform with a divide-by-two output at 5 MHz.
Determine 9 Oscilloscope waveform with a divide-by-two output at 50 MHz.
Determine 10 shows the output of the oscillator/inverter at 100 MHz. Determine 11 reveals the three.4 ns oscillator/inverter output pulse.
Determine 10 Oscilloscope waveform with the oscillator output at 100 MHz.
Determine 11 Oscilloscope waveform with a 3.4-ns oscillator pulse.
The info
So, listed below are the info.
The 2 inverters in parallel didn’t work on this software. This was mounted by eliminating certainly one of them and placing a bigger resistor in sequence with the output of the remaining one to scale back the present load on it.
The excessive sensitivity of the circuit to the enter voltage presents a problem in follow. Producing a sufficiently quiet enter voltage is troublesome.
Battery operation supplies some assist, however this presents its personal challenges in follow. Noise on the 5-V provide is a associated drawback. The provision for the second divide-by-two circuit, U7, have to be tightly regulated and very freed from noise and ripple to reduce jitter on the oscillator sign.
And, as famous above, some modifications within the values of a number of elements had been essential to get acceptable operation.
Lastly, extra correct voltage-versus-frequency operation at decrease frequencies would require extra cautious engineering, if desired. I go away this to the consumer to work this out, if crucial.
At this level, I’m happy with the circuit as it’s (I really feel that it’s time to take a break!).
Some strategies for improved outcomes
The circuit is compromised by the problem to make it work with a single 5-V provide. It will be much less difficult if separate, well-regulated, well-filtered provides had been used for U1/U2, for instance, a 14 V regulated all the way down to 11 V for the optimistic provide, and a destructive 5 V regulated all the way down to -2.5 V (use linear regulators for each provides!)
The enter may then vary from 0 to 10 V, which would scale back the enter sensitivity by an element of two and make it simpler to design quieter provides for the enter amplifier and current-to-voltage circuits, U1/U2.
On the decrease frequencies, some investigation must be executed to show the causes of the nonlinearity in that frequency vary, and to point modifications that may enhance the circuit operation.
An alternative choice can be to separate the operation into two ranges, equivalent to 100 kHz to 1 MHz and 1 MHz to 100 MHz.
Closing reality
The operation of the circuit is fairly spectacular when the circuit is modified as recommended. I feel actualizing an oscillator that gives an output from 200 kHz to 113 MHz is kind of a exceptional end result. Because of the late Jim Williams [2] and to the energetic Stephen Woodward [3] for main the way in which to the implementation of this circuit!
Jim McLucas retired from Hewlett-Packard Firm after 30 years working in manufacturing engineering and on the design and take a look at of analog and digital circuits.
References/Associated Content material
- A simulated 100-MHz VFC
- 1-Hz to 100-MHz VFC options 160-dB dynamic vary
- 100-MHz VFC with TBH present pump
- Take-Again-Half precision diode cost pump
The submit My 100-MHz VFC – the {hardware} model appeared first on EDN.
