Location: Bengaluru and Hyderabad
Firm: Cadence
- Improvement, automation and upkeep of EDA flows and scripts for bodily implementation
- Develop TFM to optimise PPA for IP’s and Delicate Controllers
- PPA characterisation and optimisation of stream for performance-oriented and power-oriented best-in-class IP cores in superior course of nodes, on TSMC, Intel, Samsung and Rapidus Foundries
- Handle regression infrastructure that tracks high quality of the RTL/stream growth in addition to the PPA of the important thing designs.
- Digital design implementation utilizing Cadence EDA instruments – Genus, Innovus, Conformal, Litmus, Tempus, Voltus, Certus, Pegasus and different backend instruments
Required expertise
- Academic Qualification: MS/MTech/BE/ BTech in Electronics from reputed institutes
- Bodily design expertise in ASIC design atmosphere
- Ought to have information of full ASIC Design Circulate, together with Synthesis, Bodily Designing, Timing Evaluation, Energy Evaluation and Formal Verification
- Ought to have wonderful management, communication, analytical and problem-solving expertise
- Ought to be self-motivated and good crew participant
