Famous reverse engineer Ken Shirriff has peered deeper into the 386 processor than anybody outdoors Intel, courtesy of a 3D computed tomography (CT) scan carried out by Lumafield — revealing the complexity that lies inside the package deal.
“Intel launched the 386 processor in 1985, the primary 32-bit chip within the x86 line,” Shirriff explains. “This chip was packaged in a ceramic sq. with 132 gold-plated pins protruding from the underside, becoming right into a socket on the motherboard. Whereas this package deal could seem boring, much more is happening inside it than you would possibly anticipate. Lumafield carried out a 3D CT scan of the chip for me, revealing six layers of advanced wiring hidden contained in the ceramic package deal. Furthermore, the chip has practically invisible steel wires linked to the perimeters of the package deal, the spikes beneath. The scan additionally revealed that the 386 has two separate energy and floor networks: one for I/O [Input/Output] and one for the CPU’s logic.”
It is a 386, however such as you’ve by no means seen it earlier than: Lumafield’s CT scanners reveal the chip’s interior workings. (📷: Ken Shirriff)
The 80386, later i386, was Intel’s third-generation entry within the x86 vary, launched in October 1985 and never formally discontinued till September 2007. Constructing upon the 286, the 386 supplied an extended pipeline and a 32-bit structure with three working mode: actual mode, protected mode, and digital mode — the latter permitting the person to run actual mode packages in a protected surroundings, if suitable.
When reverse engineers take a look at built-in circuits, it is usually the silicon die at their coronary heart that’s of curiosity — the half that comprises all of the transistors that make the factor tick. The package deal during which it is put in is often of little concern, with every thing from the bond wires outwards being ignored — however Lumafield’s 3D scan allowed Shirriff to look past the de-encapsulated die and see how the tiny bond wires make it to the chunky pins mating the chip to its motherboard.
Finding out the scan Shirriff found an surprising variety of connectivity layers, comprised of six energy planes throughout two distinct energy networks plus the sign layers. “The pins are linked to the package deal’s shelf pads by way of steel traces,” Shirriff notes, “spectacularly coloured within the CT scan. (These traces are surprisingly large and free-form; I anticipated narrower traces to cut back capacitance.) Bond wires join the shelf pads to the bond pads on the silicon die.”
The scan offers an perception into the ceramic packaging which surrounds the silicon die. (📷: Ken Shirriff)
“What shocked me most concerning the scans,” Shirriff provides, “was seeing wires that stick out to the perimeters of the package deal. These wires are used throughout manufacturing when the pins are electroplated with gold. As a way to electroplate the pins, every pin should be linked to a unfavorable voltage so it might probably perform as a cathode. That is completed by giving every pin a separate wire that goes to the sting of the package deal.”
The complete write-up is on the market on Shirriff’s weblog, together with an interactive graphic exhibiting completely different layers from the scan.
