The 16-bit DACs are a de facto customary for top DC accuracy and precision area conversion, however surprisingly few are totally 16-bit (0.0015%) exact. Even when described as “excessive precision,” some have inaccuracy and integral nonlinearity (INL) that considerably exceed 1 LSB. The TBH PWM-based design detailed right here, against this, has inherent 16-bit DC accuracy and integral linearity restricted solely by the standard of the voltage reference. And it will get them with out fancy, expensive, high-accuracy parts (e.g., no 0.0015% resistors want apply).
Wow the engineering world along with your distinctive design: Design Concepts Submission Information
Determine 1 reveals its underlying nonlinearity-correcting Take-Again-Half (TBH) topology, as defined in: “Take again half improves PWM integral linearity and settling time.”
Determine 1 The INL is canceled by the TBH topology.
Determine 1 depends on two differential relationships that successfully subtract out (take again) integral nonlinearity and attenuate ripple.
- For sign frequencies lower than or equal to the reciprocal of settling time = 1/Ts (together with DC) Xc >> R and Z = 2(Xavg – Yavg/2).
- For frequencies larger than or equal to Fpwm, Xc << R and Z = Xripple – Yripple.
As a result of just one change drives node Y whereas two in parallel drive X, INL on account of change loading at Y is twice that at X. Due to this fact, since Z = 2(Xavg – Yavg/2), A1’s differential RC community actively subtracts (takes again) the INL error element, leading to (theoretically) zero web INL.
Determine 2 illustrates how these components can match collectively in a sturdy 16-bit DAC circuit design. Right here’s the way it works.
Determine 2 TBH precept sums two 8-bit PWM alerts in a single 16-bit DAC = Vref(MSBY+LSBY/256)/256. The asterisked resistors are 0.25% precision varieties. It’s assumed that the PWM frequency (Fpwm) is ~10 kHz.
Two 8-bit decision PWM alerts with a rep price of ~10 kHz function inputs, one for essentially the most important byte (MSBY) of the setting and the opposite for the least important byte (LSBY). The MSBY sign drives R2 and R3, whereas the LSBY drives the R4, R5, and R7 community. The (R4+R5+4R7)/(R2+R3) = 256:1 ratio of the summing community accommodates the relative significance of the PWM alerts. It additionally allows true 16-bit (15 ppm) conversion precision and differential nonlinearity (DNL) from solely 8-bit (2500 ppm) resistor matching.
R6C3 suppresses small nanosecond period ripple spikes on A1’s output attributable to the super-fast output transitions of the U1 switches leaking previous A1’s 10 MHz gain-bandwidth product.
The final word conversion accuracy is restricted nearly solely by the 5-V voltage reference high quality, so this ought to be a premium element. Its job is made a little bit bit (pun) simpler by the truth that the utmost present drawn by U1 is a modest 640 µA, which permits for true 16-bit INL with reference impedances as much as 0.11 Ω. A most reference loading happens at MSBY obligation issue = 50%. The loading falls to close zero at Df = 0 and 100%.
The utmost ripple amplitude additionally happens at 50%. The output ripple and DAC settling time are illustrated because the pink curve in Determine 3.
Determine 3 Settling time to full precision requires ~100 PWM cycles = 10 ms for Fpwm = 10 kHz.
Stephen Woodward’s relationship with EDN’s DI column goes again fairly a great distance. Over 100 submissions have been accepted since his first contribution again in 1974.
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