A brand new software program combines connectivity, scalability and data-driven synthetic intelligence (AI) capabilities to push the boundaries of the IC verification course of and make chip design groups extra productive. Questa One goals to handle the verification productiveness hole for big, advanced designs spanning IP to IC to methods.
The steadily growing complexity of 3DICs, chiplet-based designs, and software-defined architectures is additional compounded by a crucial expertise scarcity and rising calls for for enhanced safety and decrease energy consumption. “Questa One makes use of new technical advances to ship the quickest practical, fault, and formal verification engines accessible,” mentioned Abhi Kolpekwar, VP and GM of digital verification applied sciences at Siemens EDA.
Determine 1 Questa One strives to redefine IC verification from a reactive course of into an clever, self-optimizing system. Supply: Siemens EDA
A latest Wilson Analysis Group survey means that one in seven IC tasks achieves first-time silicon success. Chris Giles, director of product administration for static and formal at Siemens EDA, calls this a jaw-dropping and staggering drop. “Our strategy is to allow engineers to do extra with much less, with not simply quicker engines but in addition quicker engineers with fewer workloads,” he mentioned.
Determine 2 Here’s a view of the decline in first-time silicon success and the rise in FPGA bugs. Supply: Wilson Analysis Group
Giles spoke with EDN to clarify the expertise fundamentals of this new verification instrument.
Quest One’s three tenets
Giles mentioned that Questa One has been developed round three core rules:
- Scalable verification: It permits engineers to hurry verification closure. Giles famous that the semiconductor business is struggling to sort out giant designs. “That’s why we see a decline in first-time silicon success,” he added. “Chip designs are getting so giant that it’s tough to confirm them in a single piece.” Questa One verification goals to permit engineers to work on giant chip designs.
- Knowledge-driven verification: It leverages information for AI-powered analytics to convey new insights and to enhance verification productiveness. “It collects datasets that permit verification instruments to both make suggestions or instantly determine what to do subsequent and do it productively,” mentioned Giles.
- Linked verification: Questa One connects EDA instruments and verification IP to kind a cohesive ecosystem for strong verification, validation, and check operations. In different phrases, it makes use of a broad set of applied sciences and analyses to offer insights and uncooked verification energy.
Determine 3: Questa One choices are proven with three essential worth propositions summed up on the backside. Supply: Siemens EDA
Quest One’s 4 elements
Questa One has the next focus areas:
- Questa One simulator: This simulator engine is constructed from the bottom up. It performs practical and fault simulation for RTL, GLS, and DFT purposes with parallel processing and profiling add-ons.
- Questa One SFV: The stimulus-free verification (SFV) resolution delivers person productiveness by synergistic combos of static and formal analyses, AI, automation, and parallelization. “The present static and formal expertise may be very fragmented, difficult excessive productiveness,” Giles mentioned. “SFV integrates static and formal analyses, AI, and parallelization to handle this problem.”
- Questa One verification IQ: It’s a protection resolution that makes use of generative, analytic, and prescriptive AI to drive verification closure quicker with fewer workloads. “It options an clever interface that gives perception into the complete verification ecosystem,” Giles added.
- Questa One Avery VIP: The answer, based mostly on Avery’s high-quality VIP and high-coverage compliance check suites (CTS), provides protocol-aware debug and protection analytics to assist enhance productiveness. It helps 3DIC and chiplet verification from IP to system-on-chip (SoC) design.
Determine 4 4 essential elements of Questa One embrace a simulator, a static and formal verification resolution, a verification intelligence protection evaluation resolution, and an Avery identifier. Siemens EDA
Questa One in works
Semiconductor IP provider Rambus acknowledged an improved verification expertise in managing information middle workloads like generative AI whereas implementing IPs for PCIe, CXL, and HBM interfaces. Rambus significantly talked about Questa One’s simulation, static and formal evaluation, and verification IP applied sciences.
Then there’s Arm, which used Questa One simulator to cut back regression time in its newest AArch64 structure. “The Questa One verification resolution has improved our verification productiveness throughout conventional on-premises and cloud deployments,” mentioned Karima Dridi, head of productiveness engineering at Arm.
MediaTek, one other early person of Questa One, has utilized its formal verification and simulation applied sciences. “Questa One Property Help makes use of generative AI to avoid wasting us weeks of engineering time, and Questa One Regression Navigator predicts which simulation exams are most certainly to fail, runs them first, and saves days of regression and debugging time,” mentioned Chienlin Huang, senior technical supervisor of Connectivity Expertise Division at MediaTek.
Questa One claims to yield step-function positive aspects in sensible regression, sensible evaluation, sensible engine, and sensible debug domains. Design testimonials from Arm, MediaTek, and Rambus are a great begin.
Associated Content material
- How Do You Confirm IC Efficiency?
- Combine instruments for efficient verification
- The profile of a data-driven IC design verification instrument
- Why verification issues in network-on-chip (NoC) design
- IC design: A brief primer on the formal methods-based verification
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