Location: Bengaluru
Firm: Broadcom
Job Description
Candidate ought to have excellent expertise in Bodily design actions of the block and SoC stage. Ought to be effectively skilled in floor-planning, partitioning, placement, clock tree synthesis, route, bodily verification and all signoff checks closure.
Expertise with instruments comparable to Innovus/Encounter, ICC, Caliber, LEC, Primetime and many others is extremely fascinating. Full chip tape out expertise based mostly on 5nm/7nm/16nm applied sciences is most well-liked.
Candidate could be required to work on numerous phases of SOC bodily design actions of prime stage & block stage – floor-planning, partitioning, placement, clock tree synthesis, route, bodily verification (LVS/DRC/ERC/Antenna and many others).
Ought to have wonderful problem-solving expertise to assist with congestion decision and timing closure. Candidate ought to be capable to meet congestion, timing and space metrics of design. Could be required to do equivalence checks, STA, Crosstalk delay evaluation, noise evaluation, and energy optimisation. Ought to be capable to implement timing and useful ECOs.
On this function, the Engineer will apply Broadcom’s confirmed design methodology and milestone movement to fulfill Broadcom’s rigorous standards for reaching Proper-first-time silicon.
Candidate ought to be capable to work independently and information different group members. Ought to be skilled in working in a worldwide group and dynamic surroundings.
Ought to possess the power to study and adapt to new instruments and methodologies. Wonderful communication talent is a should.
