Past 300 Layers of Reminiscence
The race to make denser, more-powerful 3D NAND flash reminiscence has led to very large innovation but additionally new manufacturing challenges. Taller devices-three-hundred-plus layers-could be threatened in yield, efficiency, and reliability attributable to constructive-tier bending and materials collapse. On this sense, these challenges come from stress mismatches in alternating stacks of silicon nitride (SiN) and oxide (TEOS) layers that represent this reminiscence construction.
To grasp and remedy the issue, the Semiverse Options staff used SEMulator3D digital Design of Experiments (DOE) to copy, measure, and analyze stress-induced deformation within the fabrication course of. The outcomes emphasize the essential consideration of stress administration and materials properties in realizing manufacturable high-layer-count NAND architectures.
Understanding How 3D NAND Is Constructed
It achieves increased densities in 3D NAND by stacking SiN and oxide layers vertically in a staircase association. Contacts are etched by means of such tall stacks to succeed in underlying transistors, and slit etchings divide the construction into practical reminiscence blocks.
Till SiN will be changed by conductive metallic, an oxide cantilever is briefly shaped: it’s anchored at one finish whereas being unsupported on the different finish. This relatively fragile construction more and more turns into weak because the variety of layers grows, increasing from ~550 nm at 200 layers to ~700 nm at 300 layers. Numerous contributors to tier collapse are as follows:
- Stress and pressure mismatches between SiN and oxide
- Floor pressure throughout SiN removing
- Cantilever size and geometry
What the Digital Research Revealed
Utilizing SEMulator3D’s stress evaluation instruments, the staff carried out two DOE research to characterize how stress might evolve with tier bending and collapse.
Key findings from the primary DOE:
- SiN Stiffness (Younger’s Modulus, Ey) and oxide thickness are the dominant variables influencing stress-based deformation.
- Current at low Ey values (70 GPa) attributable to minimal displacement.
- At 125 GPa, collapse occurred at longer cantilever lengths (700 nm), particularly with thinner oxides.
- At 256 GPa, extreme displacement and voiding occurred throughout all take a look at situations.
- Growing oxide thickness improved resistance however didn’t get rid of failure dangers.
The second DOE in contrast the results of intrinsic SiN stress (compressive vs. tensile). Outcomes confirmed compressive SiN induced bigger displacements, widening the vary of potential collapse.
The manufacturing implications
These research current apparent engineer strategies that may be employed to maximise yields in ultra-high-layer NAND:
- The SiN and oxide stress values have to be matched and hopefully lowered.
- Shorten cantilever size by designing an etch profile.
- If doable, improve oxide thickness to stabilize the stack.
Via digital simulation of those interactions, SEMulator3D engineers have the power to comprehend the method modifications that truly matter with out being solely reliant on costly experimental work on the precise silicon.
Conclusion
With NAND flash closing in on 300 layers and extra, tier bending and collapse stay edge manufacturing threats. Stress analyses and digital DOE research by the Semiverse staff have revealed that exacting management of fabric properties and stack geometry is vital to each securing yields and shortening time to market.
With the SEMulator3D platform from Lam Analysis, chipmakers achieve a robust predictive lens serving to remodel potential failure factors into alternatives for sturdy, scalable reminiscence innovation.
(This text has been tailored and modified from content material on Lam Analysis.)
