Like several profitable system-on-chip (SoC) effort, a multi-die system-in-package (SiP) mission should begin with a sound system design. However then what? Are the steps within the SiP design move totally different from the levels in an SoC design? What is important to make sure that a 2.5D or 3D SiP might be functionally appropriate, throughout the energy, efficiency, and value specs, and that will probably be manufacturable?
The simplest solution to reply these questions is to explain the multi-die design course of now we have developed at Faraday by way of our participation in SiP designs with our shoppers.
Co-design from the beginning
Ideally, the SiP specialists might be concerned within the design from the early levels. Even when the design is only a block-level sketch on a serviette, it’s not too early to start discussing how the IP blocks might be distributed among the many dies, and what the implications might be for the finished SiP (Determine 1).
Determine 1 Collaboration on a SiP design can start with the shopper’s number of chiplets and proceed by way of to a production-ready design. Supply: Faraday Expertise Corp.
A 2.5D or 3D design provides one or two extra ranges to the interconnect hierarchy between the quick, environment friendly, and dense on-die routing and the sluggish, power-hungry, and sparse board-level routing. First, superior packaging supplies a silicon interposer for interconnecting the dies.
This degree of interconnect is dense, though far much less dense than the decrease steel layers on a die, and it’s comparatively energy-efficient, low-latency, and high-bandwidth, albeit inferior to on-die steel. Stacking dies—going 3D—provides one other degree to the hierarchy: direct connections between dies, through-silicon vias, and microbumps or hybrid bonding. This degree is best than interposer connections, however nonetheless not equal to on-die connections.
The problem in partitioning the multi-die design is that the constraints of every degree of interconnect will impose themselves on no matter alerts are being routed by way of that degree. Thus, selecting what alerts to hold and the place will they finally affect system energy, efficiency, and space. Subsequently, partitioning is a key choice on this course of: which IP blocks to placed on which dies.
Partitioning will decide which sign paths should be routed on which ranges of the routing hierarchy. Thus, partitioning selections will affect the benefit, issue, or impossibility of routing and timing closure on every degree. If crucial alerts are positioned on an interconnect with inadequate bandwidth or extreme latency to fulfill necessities, they may affect system efficiency.
Moreover, they may have an effect on system energy, as interconnect energy consumption will not be inconsequential on the system degree. For these causes, the sooner the SiP-design specialists interact with the system designers, the higher the ensuing design high quality is more likely to be.
Chip and SiP
There are two distinct instances to contemplate right here. In some SiP designs, all dies that can go into the SiP are already designed. The SiP group will then resolve on die placement and, probably, the order of dies in stacks, and can route the connections between dies. Nonetheless, the partitioning of features among the many dies and the places of particular person pads on every die have already been mounted. This considerably reduces the SiP design planning drawback and limits the SiP designers’ freedom.
In distinction, in some initiatives, a number of dies are designed particularly for the SiP. One in all these new dies will typically be an SoC, carrying a lot of the system performance and serving because the hub for connections throughout the SiP. In these instances, far more optimization is feasible if the die design and SiP groups work collectively. On the very least, the die and interposer designers can cooperate on the die pad location to ease the interposer structure.
Deeper cooperation can embrace optimizing the die floorplan to get the pads for crucial interconnect buses in the very best place to attenuate interconnect size and congestion. Early cooperation might affect decisions of protocols and transceivers for die-to-die connections and even rethink the partitioning.
This added freedom is effective. The comparatively lengthy latency, restricted bandwidth, and better energy consumption of interposer and package-substrate interconnect can dominate SiP efficiency. Subsequently, minor changes to a die structure that enable for vital enhancements in SiP routing may end up in substantial beneficial properties in system-level high quality of outcomes.
Interposer and package deal
The results of all this planning and co-design is an inventory of the precise location of every pad on every die and every ball on the package deal substrate, along with a routing record indicating what should connect with what. An extra important dataset comprises the signal-integrity and power-integrity necessities for every connection.
These latter specs might come from interface requirements equivalent to Common Chiplet Interconnect Specific (UCIe), Bunch of Wires (BoW), or the Excessive-Bandwidth Reminiscence (HBM) channel specs. Or they might be dictated by particular pin necessities on the dies.
Now, the two.5D/3D group should design an interposer and package deal substrate that satisfies the connection, sign, and power-integrity necessities. The design must also reduce general SiP price and guarantee manufacturability. Evidently, that is an over-constrained optimization drawback—it requires wonderful instruments and deep design expertise to get the very best outcome.
SiP analyses
Profitable routing will not be the top of this story. Earlier than the SiP design might be launched, every hint should be subjected to signal-integrity or power-integrity evaluation utilizing particular evaluation instruments, typically on the detailed degree of multiphysics instruments. The SiP design group ought to present the system designers with the SiP’s thermal and electrical traits for full thermal evaluation. Ideally primarily based on precise circuit exercise with manufacturing software program, this evaluation is commonly important to making sure the SiP’s reliability in its supposed setting.
This design move has confirmed profitable at Faraday, emphasizing early engagement amongst system designers, die design groups, and SiP designers. The latter group should possess the talents and expertise to acknowledge potential points early, earlier than there’s enough knowledge for full evaluation, when a partitioning selection, die placement, or pad location might trigger hassle downstream.
The SiP group will need to have the talents and instruments to design, optimize, and analyze the interposer and package deal substrate. As necessary as that is, the group will need to have shut relationships with foundry, meeting, and check companions to make sure the SiP might be manufacturable in its supposed provide chain (Determine 2).
Determine 2 Shut collaboration between design groups, silicon foundries, and OSAT companions is important for the profitable manufacturing of a multi-die machine. Supply: Faraday Expertise Corp.
To return to our unique query: sure, extra steps, expertise, and relationships are mandatory to make sure the success of an SiP. These wants make selecting a design accomplice some of the crucial selections the administration will make on a SiP mission.
Subsequent, shut cooperation between the design groups, the silicon foundry, and the OSAT companions is important to supply a profitable multi-die machine.
Wang-Jin Chen leads Faraday’s Design Growth Methodology group, which focuses on methodology, design move, verification, and sign-off for superior package deal design.
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