HomeElectronics“Flip ON Flop OFF” for 48-VDC methods with high-side switching

“Flip ON Flop OFF” for 48-VDC methods with high-side switching



“Flip ON Flop OFF” for 48-VDC methods with high-side switching

My Design Thought (DI), “Flip ON Flop OFF for 48-VDC methods,“ was revealed and referenced Stephen Woodward’s earlier “Flip ON Flop OFF” circuit. Different DIs revealed on this subject material had been for voltages lower than 15 V, which is the voltage restrict for CMOS ICs, whereas my DI was meant for greater DC voltages, usually 48 VDC. On this earlier DI, the bottom line is switched, which suggests the enter and output grounds are completely different. That is acceptable to many purposes because the voltage is small and won’t require earthing.

Nonetheless, some readers within the feedback part wished a scheme to change the excessive aspect, retaining the bottom the identical. To fulfill such a requirement, I modified the circuit as proven in Determine 1, the place enter and output grounds are saved the identical and switching is completed on the constructive line aspect.

Determine 1 VCC is round 5 V and needs to be linked to the VCC of the ICs U1 and U2. The grounds of ICs U1 and U2 must also be linked to floor (connection not proven within the circuit). Switching is completed within the excessive aspect, and the bottom is identical for the enter and output. Be aware, it’s crucial for U1 to have a warmth sink.

Wow the engineering world together with your distinctive design: Design Concepts Submission Information

On this circuit, the voltage dividers R5 and R7 set the voltage at round 5 V on the emitter of Q2 (at VCC). This voltage is utilized to ICs U1 and U2. A exact setting is just not vital, as these ICs can function from 3 to fifteen V. R2 and C2 are for the ability ON reset of U1. R1 and C1 are for the push button (PB) change debounce.

 While you momentarily push PB as soon as, the Q1-output of the U1 counter (not the Q1 FET) goes HIGH, saturating the Q3 transistor. Therefore, the gate of Q1 (PMOSFET, IRF 9530N, VDSS=-100 V, IDS=-14 A, RDS=0.2 Ω) is pulled to floor. Q1 then conducts, and its output goes close to 48 VDC.

Because of the 0.2-Ω RDS of Q1, there shall be a small voltage drop relying on load present. While you push PB once more, transistor Q3 turns OFF and Q1 stops conducting, and the voltage on the output turns into zero. Right here, switching is completed on the excessive aspect, and the bottom is saved the identical for the enter and output sides.

If galvanic isolation is required (this may occasionally not at all times be the case), chances are you’ll join an ON/OFF mechanical change previous to the enter. On this topology, on-load switching is taken care of by the PB-operated circuit, and the ON/OFF change switches zero present solely, so it doesn’t must be cumbersome. You’ll be able to choose a change that passes the required load present. Whereas switching ON, first shut the ON/OFF change after which function PB to attach. Whereas switching OFF, first push PB to disconnect and function the ON/OFF change.

Jayapal Ramalingam has over three a long time of expertise in designing electronics methods for energy & course of industries and is presently a contract automation marketing consultant.

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The submit “Flip ON Flop OFF” for 48-VDC methods with high-side switching appeared first on EDN.

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