A brand new 3D chip stacking technique developed in Japan guarantees to revolutionize AI and high-performance computing with sooner information switch, diminished energy consumption, and compact integration.
In a big leap for semiconductor know-how, researchers from Science Tokyo have launched a complicated 3D chip integration strategy geared toward delivering excessive reminiscence bandwidth and ultra-low energy consumption for next-generation computing methods. Their work was just lately showcased on the 2025 IEEE Digital Elements and Expertise Convention (ECTC).
Historically, system-in-package (SiP) designs use 2D chip placement by way of solder bumps, which restricts additional miniaturization and efficiency scalability. To deal with these challenges, the crew developed a cutting-edge chip integration framework named BBCube, primarily based on a 2.5D/3D stacking strategy. This structure options processing items (xPUs) stacked immediately above DRAM modules, enabling shorter interconnects and sooner information switch.
To make this structure viable, the researchers tackled three essential areas. First, they created a face-down chip-on-wafer (COW) bonding course of utilizing inkjet know-how and selective adhesives. This enabled the exact and speedy mounting of over 30,000 otherwise sized chips on a 300 mm waffle wafer with chip-to-chip gaps as slender as 10 micrometers—and bonding occasions of underneath 10 milliseconds per chip.
Second, to help the mechanical and thermal calls for of ultra-thin stacked wafers, they formulated a novel adhesive named DPAS300, constructed on an natural–inorganic hybrid construction. This materials gives robust thermal stability and can be utilized throughout each chip-on-wafer and wafer-on-wafer bonding processes.
Lastly, to make sure steady energy supply and high-speed communication throughout the stack, the crew carried out a brand new energy distribution freeway. This consists of embedded capacitors between layers, through-silicon vias, and redistribution layers to cut back power loss and suppress energy noise to beneath 50 mV.
By lowering information transmission power to only 5–20% of typical methods, this 3D integration know-how opens doorways for extra environment friendly AI {hardware}, HPC methods, and edge units. The improvements from Science Tokyo might mark a foundational shift in how chips are packaged and powered within the AI-driven computing period.
