Location: Hyderabad
Firm: STMicroelectronics
Drive to “zero-defect”. Duties embody the event of a verification check bench, improvement of verification elements, check case improvement for simulation, debugging failures and creating simulation instances for numerous research. As an skilled skilled, work with cutting-edge verification methodologies on standalone IPs, Subsystem degree and SoC degree.
Duties Embody, However Not Restricted To
- Verification planning, reviewing, structure definition, Verification check bench improvement and implementation
- Growth of verification check bench elements equivalent to drivers, screens, response checkers in addition to use most superior UVM VIPs.
- Growth of direct and constrained-random stimulus, Understanding and evaluation of RTL code, purposeful, assertion protection outcomes.
- Sturdy expertise in debugging, failure re-creation and root trigger evaluation
- Gate degree simulations (unit delay, and with SDF annotated) and its debugging
- Check sample debugging and testing for verification and computerized testers
- Steady enchancment of verification strategies/instruments/flows/processes along with EDA companions. Discovering cost-effective and progressive verification methods
- Assertion-based verification and automatic testcase/situation technology (eg. Perspec) can be a plus
Technical background/Key Expertise
- Qualification: Bachelors/Masters in Electronics/Pc Science
- VHDL/Verilog, System Verilog, C language
- OVM/UVM, class-based verification methodologies
- Deep Understanding of ARM multicore-based SoC structure
- AMBA – AXI, AHB, APB bus protocols
- NIC/FlexNOC interconnect structure information
- In-depth information or ARM-based core. Understanding of Hint and Debug infrastructure.
- Data of reminiscence controller and NVM can be a plus
- Scripting proficiency – PERL, Python, UNIX/LINUX
- Simulation instruments like – Xcelium/VCS/Questasim. Perspec. Planning and regression instruments like VManager
- Publicity to any of defect and model administration instrument
