Cadence has introduced the primary DDR5 12.8-Gbps MRDIMM Gen2 reminiscence IP subsystem, that includes a PHY and controller fabricated on TSMC’s N3 (3-nm) course of. The design was hardware-validated with Gen2 MRDIMMs populated with DDR5 6400-Mbps DRAM chips, reaching a 12.8-Gbps knowledge charge—doubling the bandwidth of the DRAM gadgets. The answer addresses rising reminiscence bandwidth calls for pushed by AI workloads in enterprise and cloud knowledge middle purposes.
Primarily based on a silicon-proven structure, the DDR5 IP subsystem supplies ultra-low latency encryption and superior RAS options. It’s designed to allow the next-generation of SoCs and chiplets, providing versatile integration choices, in addition to exact tuning of energy and efficiency.
Mixed with Micron’s 1γ-based DRAM and Montage Know-how’s reminiscence buffers, Cadence’s DDR5 MRDIMM IP delivers a high-performance reminiscence subsystem with doubled bandwidth. The PHY and controller have been validated utilizing Cadence’s DDR Verification IP (VIP), enabling speedy IP and SoC verification closure. Cadence studies a number of ongoing engagements with main clients in AI, HPC, and knowledge middle markets.
For extra data, go to the DDR5 MRDIMM PHY and controller web page.
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