I’ve just lately revealed Design Concepts (DIs) exhibiting circuits for linear PWM programming of ordinary bucking-type regulators in purposes requiring an output span that may swing beneath the regulator’s sense voltage (Vsense or Vs). For instance: “Easy PWM interface can program regulators for Vout < Vsense.”
Wow the engineering world together with your distinctive design: Design Concepts Submission Information
Objections have been raised, nonetheless, that such circuits entail a major lack of programming analog accuracy as a result of they depend on including a voltage time period usually derived from an out there voltage (e.g., logic rail) supply. Subsequently, they need to be prevented.
The argument depends on the truth that such sources usually have accuracy and stability which are considerably worse (e.g., ±5%) than these of regulator inner references (e.g., ±1%).
However is that this objection really true, and in that case, how severe is the issue? How a lot of an accuracy penalty is definitely incurred? This DI addresses these questions.
Determine 1 exhibits a primary topology for sub-Vs regulator programming with present expressions as follows:
A = DpwmVs/R1
B = (1 – Dpwm)(Vl – Vs)/(R1 + R4)
The place A is the first programming present and B is the sub-Vs programming present giving an output voltage:
Vout = R2(A + B) + Vs
Determine 1 Primary PWM regulator programming topology.
Inspection of the A and B present expressions exhibits that when the PWM obligation issue (Dpwm) is ready to full-scale 100% (Dpwm = 1), then B = 0. That is as a result of (1 – Dpwm) time period.
Subsequently, there may be no error contribution from the logic rail Vl at full-scale.
At different Dpwm values, nonetheless, this comfortable circumstance now not applies, and B turns into nonzero. Thus, Vl tolerance and noise degrade accuracy, no less than to some extent. However, by how a lot?
The best solution to tackle this significant query is to guage it as a believable instance of Determine 1’s normal topology. Determine 2 gives some concrete groundwork for that by including some instance values.
Determine 2 Placing some meat on Determine 1’s naked bones, including instance values to work with.
Assuming good resistors, nominal R1 currents are then:
A = Dpwm Vs/3300
B = (1 – Dpwm)(Vl – Vs)/123300
Vout = R2(A + B) + Vs = 75000(A + B) + 1.25
Then, making the (extremely pessimistic) assumption that reference errors stack up because the sum of absolute values:
Aerr = Dpwm 1percentVs/3300 = Dpwm 3.8µA
Berr = (1 – Dpwm) (5% 3.3v + 1% 1.25v)/123300 = (1 – Dpwm) 1.44µA
Vout complete error = 75000(Dpwm 3.8µA + (1 – Dpwm)1.44µA)) + 1% Vs
The ensuing Vout error plots are proven in Determine 3.
Determine 3 Vout error plots the place the x-axis is Dpwm and y-axis is Vout error. Black line is Vout = Vs at Dpwm = 0 and pink line is Vout = 0 at Dpwm = 0.
Conclusion: Error does enhance within the decrease vary of Vout when the Vout < Vsense function is integrated, however any distinction utterly disappears on the high finish. So, the selection activates the utility of Vout < Vsense.
Stephen Woodward’s relationship with EDN’s DI column goes again fairly a good distance. Over 100 submissions have been accepted since his first contribution again in 1974.
Associated Content material
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- PWM nonlinearity that software program can’t repair
- One other PWM controls a switching voltage regulator
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