Among the many Highlights had been Particular Periods Detailing the Standing and Future Instructions of Know-how in Key Areas
The 75th annual 2025 IEEE Digital Elements and Know-how Convention (ECTC), held on the Gaylord Texan Resort & Conference Middle right here Might 27-30, had report attendance, a report variety of paper submissions/displays, report worldwide and pupil participation, and a report variety of exhibitors in a sold-out exhibition corridor:
- 2,518 attendees, the best within the convention’s 75-year historical past and a major improve over the two,008 who attended final 12 months, which itself was a report.
- The variety of abstracts submitted was the best ever (775), as had been the 390 technical papers offered in 36 oral and 5 interactive presentation periods, together with one devoted to college students.
- A number of paper displays attracted greater than 600 attendees, as periods on matters of intense trade curiosity – resembling hybrid bonding– had been standing-room solely.
- 16 skilled growth programs had been attended by 596 members.
- There have been audio system from greater than 20 international locations globally.
- There was a report degree of trade help, with 51 company sponsors and 138 cubicles within the exhibit corridor.
Among the many highlights had been 11 Particular Periods. In these, panels of trade consultants mentioned the current standing and future roadmaps of applied sciences important for synthetic intelligence (AI), high-performance computing (HPC) and different fast-growing, evolving functions.
“Superior chip packaging applied sciences are important for the event of the electronics trade, and the ECTC convention has lengthy been the world’s main discussion board for developments in microelectronics packaging and element science and know-how,” mentioned Przemyslaw Gromala, ECTC 2025 Program Chair and Chief Skilled/R&D Mission Chief at Robert Bosch GmbH. “ECTC serves as a collaborative international platform for exploring cutting-edge developments in microelectronic packaging, fostering innovation and addressing key trade challenges. This 12 months’s Particular Periods supplied a wealthy choice of compelling matters and knowledgeable panelists.”
Listed here are highlights from three of the ECTC 2025 Particular Periods:
Superior Supplies for Enabling Co-Packaged Optics Integration – This Particular Session was co-Chaired by Karan Bhangaonkar (Google) and Vidya Jayaram (Chipletz). Panelists had been Mark Gerber (ASE), Z. Rena Huang (Rennselaer Polytechnic Inst.); Padraic Morrissey (Tyndall Nationwide Inst.), Kumar Abhishek Singh (Intel) and Christopher Striemer (AIM Photonics).
As fashionable computing strives for larger efficiency, co-packaged optics or CPO (i.e., the combination of optics and electronics on a substrate) is rising as an answer to fulfill computing/communication calls for for prime bandwidth at low energy. The improvements, challenges and future wants to appreciate CPO know-how had been mentioned on this Particular Session.
Gerber from ASE gave an outline of the system necessities which are driving CPO materials issues, noting that warmth can have vital results on photonic built-in circuits. He additionally recognized different points that improve thermal sensitivities in CPO architectures, resembling flux outgassing, and described why the order wherein meeting steps happen additionally has an influence.
Huang from RPI mentioned that whereas a lot work is going down to grasp and handle CPO packaging issues, way more progress is required, particularly for AI chiplets for large-language fashions (LLMs), the place the important thing issues are velocity, energy and effectivity. She mentioned the likelihood to construct optical networks on optical interposers/wafers/panels, noting that giant chiplets might be optically related with optical interposers, utilizing optical waveguides to scale back loss.
Morrissey from Tyndall mentioned that for optimum CPO efficiency, the optics have to be moved nearer to the sting of compute, and glass has nice potential to be used as a substrate as a result of it’s optically clear, has good RF habits, and lends itself to fabricating high-quality vias. Glass can also work past wafers and with actually giant panels, he mentioned, and might result in pluggable connectivity. Nevertheless, he famous that warmth is a matter with glass.
Singh from Intel mentioned CPO isn’t simply fascinating, it’s completely essential to scale-up superior packaging. He famous that CPO permits each edge and vertical interconnects, which means there are numerous areas the place supplies come into play. He mentioned that whereas CPO architectures face distinctive challenges – resembling overseas particles blocking the sunshine path – in addition they face most of the identical points as non-CPO architectures, resembling misalignment and cracks. However these challenges deliver alternatives to advance the state-of-the-art.
Striemer from Goal Photonics described why optically energetic supplies will drive CPO, and likewise outlined the necessity for passive materials improvements resembling 3D printing and novel designs like suspended constructions, though proper now it’s unclear which of them will supply essentially the most profit.
Hybrid Bonding (HB): to B, or to not B? Wants and challenges for the following decade – This Particular Session was co-Chaired by Benson Chan (Binghamton Univ.), Masha Gorchichko (Utilized Supplies) and Dishit Parekh (AMD). The panelists had been Su Jin Ahn (Samsung), Anne Jourdain (imec), Chet Lenox (KLA), Laura Mirkarimi (Adeia), Masao Tomikawa (Toray Ind.) and Brett Wilkerson (AMD).
Hybrid bonding is the important thing know-how for high-density 3D integration and superior packaging, and lately, vital developments had been made in pitch scaling, die-to-die bonding, different supplies, and low-temperature processes. However many engineering and technological challenges stay, resembling defectivity, metrology, design challenges, and price. This panel summarized current developments in HB, recognized essentially the most urgent points limiting its adoption for mainstream electronics, and outlined its seemingly growth over the following decade.
Gorchichko from Utilized famous the several types of HB (wafer-wafer, die-wafer, die-die) and mentioned that whereas HB debuted about 10 years in the past in a picture sensor from Sony, in the present day the main target is on integrating DRAM reminiscence. She mentioned that superior metrology is essential, as a result of we are actually speaking about molecular bonds, and due to this fact an understanding of all of the related chemical and mechanical necessities is required. Furthermore, to get larger yields and extra throughput, not simply higher but additionally quicker metrology is required. She famous that thermal issues are a problem with rising energy density.
Su Jin Ahn from Samsung outlined main HB know-how points and challenges. One is that the various course of steps required go away particles on the bonding floor, resulting in potential failure. One other is that for AI, the broader, thinner dies used degrade bonding and result in high quality points. She mentioned what’s wanted are superior metrology/inspection instruments and strategies, together with design/course of co-optimization for bonding. She mentioned the primary driver going ahead is the necessity to mix chip and packaging applied sciences.
Jourdain from imec emphasised the necessity for quick, dependable metrology options, and mentioned the professionals and cons of copper interconnect and barrier metals.
Lenox from KLA famous the various wants and challenges that include HB – interposers, warpage management, dielectric interface profiles, clear singulation, bonding alignment – and mentioned that whereas HB is necessary, there are different much less advanced and expensive applied sciences that may preclude the necessity for HB, resembling bridges. He additionally mentioned that HB creates a necessity for superior metrology and inspection capabilities all the way in which from the entrance finish to packaging.
Mirkarimi from Adeia centered on three areas: metrology enhancements for improved throughput and yield; the evolution of two.5D/3.5D HB packaging know-how; and thermal options for prime power-density chipsets. With regard to metrology, she famous that HB architectural complexity calls for a dependable “well being of the road” metrology protocol for all course of steps. Additionally, higher methods to grasp nanoscale topography and to detect floor defects are wanted, as are methods to transform HB to scale back prices, resembling bond power engineering. Relating to HB packaging developments and challenges, she mentioned that ultra-high bandwidth, inter-die communication at a 1µm die-to-wafer pitch would require system simplification, resembling bonding dies on to the substrate or utilizing bridge dies to interchange an interposer. For thermal administration, she described a possible cooling resolution that makes use of an built-in manifold and a chilly plate bonded to an IC, amongst different options, and which may be custom-designed to handle particular warmth maps.
Tomikawa from Toray mentioned that as the necessity to bond chips to interposers will increase, the necessity for HB processes that make use of polyimide (PI) resin will turn out to be extra obvious. That’s as a result of PI permits low-temperature, low-pressure HB processes which decrease warpage and machine harm. Many challenges stay, although – exact copper protrusion management and low-temperature copper diffusion bonding are key components for fulfillment.
Wilkerson from AMD spoke from a product perspective. He identified that HB requires advanced processing. a lot time and lots of costly fab processes, and that it might take a number of weeks to perform, which impacts an organization’s time-to-market capabilities. He mentioned thermal resistance is a crucial difficulty, and that there’s a necessity for requirements for the usage of HB for reminiscence integration with silicon.
Thermal Administration Options for Subsequent-Technology Bottom Energy Supply – This Particular Session was co-Chaired by Dwayne R. Shirley (Marvell) and Tiwei Wei (Purdue College/UCLA). The panelists had been Muhannad Bakir (Georgia Tech), Dureseti Chidambarrao (IBM) and Herman Oprins (imec).
The rising energy density and thermal challenges in superior semiconductor packaging have led to the event of bottom energy supply (BPD) know-how, the place the ability supply community is relocated from the frontside to the bottom of a silicon wafer. Whereas it enhances energy effectivity, efficiency, and design flexibility, BPD additionally introduces thermal administration challenges and the necessity for progressive cooling options. Contributors on this Particular Session mentioned the most recent developments and challenges in thermal administration for next-generation BPD.
Bakir from Georgia Tech mentioned that for 3D architectures, interlayer cooling is required, however requested, how will we allow high-density interconnect inside such a construction? He mentioned the answer is to manufacture through-silicon through (TSV) constructions with built-in cooling, electrical conductivity, and energy, utilizing vertical vias. He addressed the various points that such a design brings – facet ratios, TSV heights, and so on.
Chidambarrao from IBM mentioned that as a result of there are many subtleties with BPD architectures, decreasing the issue to necessary fundamentals and fixing it with sufficient accuracy is essential. He famous that chip complexity considerably impacts thermal conductivity, and that level-to-level variations may be fairly giant. He mentioned that an understanding of the complete chip overlay is required, as a result of there are difficult sizzling spots, and he described IBM’s technique, which is to make use of machine studying plus FEA modeling to calculate the typical properties of a number of ranges collectively. He famous that BPD points solely turn out to be worse with 3D architectures.
Oprins from imec mentioned it’s completely crucial to establish the fundamental issues with every explicit BPD structure, as a result of there are such a lot of totally different flavors of BPD.
Wei from Purdue/UCLA mentioned that bond interfaces drive thermal impacts, and he or she gave an outline of analysis into other ways to take care of this difficulty, encompassing components resembling die thickness, CMOS-compatible constructions like air gaps or glass bridges, trenches, copper/diamond microbump bonding, two-layer microchannel constructions (i.e. manifolds), and others.
