The circuit offered by Cor Van Rij for characterizing JFETs is a intelligent resolution. Noteworthy is the usage of a five-pin check socket wired to accommodate all the potential JFET pinout preparations.

This concept makes use of that socket association in a less complicated circuit. The one requirement is the supply of two digital multimeters (DMMs), which add the good thing about having a maintain perform to the measurements. Along with accuracy, the opposite targets in creating this tester had been:

• It should be easy sufficient to permit building with out a customized printed circuit board, as just one tester was required.
• Use elements available as a lot as potential.
• Accommodate each N- and P-channel units whereas utilizing a single voltage provide.
• Use a variety of provide voltages.
• Incorporate a present restrict with LED indication when the restrict is reached.

The circuit

The ensuing circuit is proven in Determine 1.

Determine 1 Characterizing JFETs utilizing a socket association. The fixture requires the usage of two DMMs.

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Q1, Q2, R1, R3, R5, D2, and TEST pushbutton S3 comprise the easy present restrict circuit (R4 is a parasitic Q-killer).

S3 provides energy to S1, the polarity reversal swap, and S2 selects the measurement. J1 and J2 are banana jacks for the DMM set to learn the drain present. J3 and J4 are banana jacks for the DMM set to learn Vgs(off). 

Observe the polarities of the DMM jacks. They’re organized in order that the drain present and Vgs(off) learn appropriately for the kind of JFET being examined—optimistic IDSS and adverse Vgs(off) for N-channel units and adverse IDSS and optimistic Vgs(off) for P-channel units.

R2 and D1 point out the incoming energy, whereas R6 offers a minimal load for the present limiter. Resistor R8 isolates the DUT from the results of DMM-lead parasitics, and R9 offers a path to earth floor for static dissipation.

Testing JFETs

Determine 2 exhibits the tester setup measuring Vgs(off) and IDSS for an MPF102, an N-channel gadget. The required values of this gadget are Vgs(off) of -8v most and IDSS of two to twenty mA. Observe that the maintain perform of the meters was used to take care of the measurements for the {photograph}. The availability for this implementation is a nominal 12-volt “wall wart” salvaged from a defunct router. 

Determine 2 The check of an MPF302 N-Channel JFET utilizing the JFET characterization circuit.

Determine 3 exhibits the present restrict in motion by setting the N-JFET/P-JFET swap to P-JFET for the N-channel MPF102. The restrict is 52.2 mA, and the I-LIMIT LED is brightly lit. 

Determine 3 The present restrict check that units the N-JFET/P-JFET swap to P-JFET for the N-channel MPF102.

John L. Waugaman’s love of electronics started after I constructed a crystal set at age 10 with my father’s assist. Incomes a BSEE from Carnegie-Mellon College led to a 30-year profession in trade designing product inspection tools and 4 patents. After being RIF’d, I spent the following 20 years as a guide specializing in analog design in industrial and navy initiatives. Now I’m retired, form of, however nonetheless designing.  It’s in my blood, I assume.

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