In April 2012, EDN printed a circuit by John Fattaruso that allows you to shortly measure the drain-source saturation present and the pinch-off voltage of each an N-JFET and a P-JFET. The pinch-off voltage (Vp) is measured by inserting a really giant resistance between the supply and the bottom. The drain-source saturation present (IDSS) is measured by inserting a small resistance between the supply and the bottom. Then, the voltage throughout this resistor is measured, and each Vp and IDSS might be calculated utilizing Ohm’s legislation. 

There’s a catch with this circuit: Since IDSS is measured throughout a non-zero resistor, there’s a deviation from the true IDSS, see Determine 1. This circuit does not likely measure level A, however truly measures level B barely earlier than this. For JFETs with decrease Vp voltages and/or larger IDSS currents, there generally is a deviation between the measured and actual IDSS worth of 5% or extra.

Determine 1 An ordinary N-JFET drain-source present vs gate-source voltage curve.

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Circuit concept

The accuracy of the circuit might be drastically elevated by making a few minor adjustments. Determine 2 reveals the essential circuit. 

Determine 2 A fundamental, improved circuit for the JFET IDSS and Vp measurement.

An astute reader will instantly see the 2 circuits’ similarities and variations. Change 1 is, once more, used to pick out between N-channel JFETs and their much less widespread sibling: P-channel JFETs.

Change 2 is used to pick out between Vp and IDSS measurement. Within the place as drawn, IDSS is measured. On this place, A1 is about up as a transimpedance amplifier. 

With the op-amp’s non-inverting enter related to floor, A1 will hold the inverting enter, and therefore the supply, to floor as effectively. This ensures that the true IDSS is measured. Resistor R3 then converts the present to a voltage that may be measured on the output of A1. 

When Change 2 is flipped to the opposite place, A1 is about up as a easy voltage follower. The pinch-off voltage that develops throughout R1 is then buffered and accessible on the output of A1.

Full implementation

Now that we have now seen the essential circuit, we will have a look at a full implementation (Determine 3). Resistor R2 limits the present that may circulation in case a JFET is inserted incorrectly. In pinch-off measurement mode, the impedances round Q1, R1 and A1 are all fairly excessive. To restrict the affect of noise, capacitor C1 is added. It’s best to maintain these wires quick and/or to construct the circuit in a shielded field. 

Determine 3 First implementation of the sensible circuit used to measure  IDSS and Vp.

Most operational amplifiers can solely supply or sink a small quantity of present. The drain-source saturation present can simply be within the tens of milliamperes. To spice up the present output capabilities of A1, a complementary bipolar transistor output stage is added. Please word that the output will not be short-circuit proof. If most popular, a easy 1 kΩ to 10 kΩ resistor might be added in collection with the output. 

With the present resistor values within the circuit, a pinch-off voltage of ±10 V might be measured and a saturation present of ~ ±100 mA. 

Though there are JFETs with giant saturation currents (suppose J109 with IDSS > 40 mA and J108 with IDSS > 80 mA!), that is merely not wanted for many JFETs. So, a variation on this circuit was developed. The pinch-off voltage remained the identical, however the saturation present was returned to 25 mA, overlaying virtually all JFET varieties. An extra requirement was that the output voltage vary for each measurements wanted to be the identical: 0 … ±5 V. This was so {that a} transferring coil meter readout could possibly be used with a single vary.

See Determine 4 for the implementation.

Determine 4 A circuit with the tailor-made measurement vary that’s fitted to most JFETs.

Learn-out

A read-out must be added to make this a whole measurement instrument. Since I’ve a big inventory of transferring coil meters, I made a decision to make use of one in all these for the read-out. To some, they might look antiquated, however they’re a pleasure to make use of and a marvel of mechanical engineering! The output might be constructive or detrimental relying on whether or not you’re measuring Vp or IDSS, and whether or not an N-type JFET or a P-type JFET is being examined. So, that is one thing that must be handled. Additionally, it might be good if there have been some form of polarity indication. See Determine 5 for the read-out circuit.

Determine 5 The readout circuit with delicate polarity indication. 

The 1-mA transferring coil meter is included within the suggestions loop across the op-amp. D3-D6 type a typical rectifier bridge in order that, unbiased of the polarity of the enter voltage, the meter is all the time fed a constructive present. 

Transistors Q1 and Q2 function a polarity indication. Optimistic voltages will activate Q1 and LED D9. LED D10 will point out detrimental voltages. 

D7,8 usually are not wanted for the rectification. Due to these diodes, the A1 output voltage should be above/under ±1.8 V earlier than any important present will circulation via the meter. This, in flip, ensures that transistors Q1 and Q2 will already activate at very low enter voltages, giving a superb polarity indication throughout the entire enter vary.

Check socket

Over time, producers have created JFETs with virtually each doable pin-out, so making a single common take a look at socket will not be so trivial. With three leads, there are 3! = 6 doable mixtures as proven in Desk 1.

Desk 1 The six doable pin-out mixtures that can be utilized for an off-the-shelf JFET.

After all, a JFET with a pin-out of S-D-G (#6) might be examined in a socket with pin-out G-D-S (#1), just by inserting it reverse within the socket. This successfully eliminates half of the doable mixtures. So we’re left with the next three, as proven in Desk 2. 

Desk 2 A discount within the variety of pin-out mixtures by merely reversing the part throughout the take a look at socket.

After a little bit of doodling, we will create a single five-pin take a look at socket that may accommodate each doable JFET pin-out as proven in Desk 3.

Desk 3 A singular 5-pin take a look at socket to accommodate all doable JFET pin-outs. 

There are two totally different variants doable; that is left as an train to the reader. The identical logic might be utilized to create common take a look at sockets for bipolar transistors, in fact.

Determine 6 The ultimate PCB implementation of the sensible JFET circuit used to measure IDSS and Vp, displaying the take a look at socket. 

In closing

Due to John Fattaruso for his glorious design concept, which sprouted this concept! All of us stand on the shoulders of the giants that got here earlier than us.

Cor van Rij blew his first fuse at 10 below the shut supervision of his father, who promptly forbade him from ever engaged on the home mains once more. He constructed his first regenerative receiver on the age of 12, and as a boy, his bed room was embellished with all kinds of antennas, and an enormous assortment of disassembled radios took up each horizontal floor. He studied electronics and graduated cum laude.

He labored as an information design engineer and engineering supervisor within the telecom trade. And has labored for nearly 20 years as a principal electrical design engineer, specializing in analog and RF electronics and embedded firmware. On daily basis is a brand new discovery!

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