Determine 1’s damaging fixed present supply has been a textbook utility for the LM337 regulator endlessly (or thereabouts). It exactly maintains a continuing output present (Iout) by forcing the OUTPUT pin to be the damaging Vadj relative to the ADJ pin. Thus, Iout = Vadj/Rs.
Determine 1 Traditional LM337 fixed damaging present supply the place Iout ≃ Vadj/Rs = 1.25/Rs.
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It has labored nicely for half a century regardless of its inflexibility. I say it’s rigid as a result of the best way you program Iout is by altering Rs. It might be laborious to consider {that a} half so mature (okay previous) because the 337 may need any new tips left to be taught, however Determine 2 teaches it one anyway. It’s a novel topology with higher agility. It leaves the resistors fixed and as an alternative applications Iout with the (a lot smaller) management present (Ic).
Determine 2 Rc sometimes >100Rs, subsequently Ic < Iout/100 and Iout ≃ -(1.25 – (IcRc))/Rs.
Rc > 100Rs permits management of present of Iout with solely milliamps of Ic. Determine 3 exhibits the thought fleshed out into a whole PWM-controlled 18 V, 1 A grounded-load damaging present supply.
Determine 3 An 18 V, 1 A, PWM-programmed grounded load damaging present supply with a novel LM337 topology. With this topology, accuracy is insensitive to produce rail tolerance. The asterisked resistors are 1% or higher and Rs = 1.25 Ω.
The PWM frequency, Fpwm, is assumed to be 10 kHz or thereabouts, if it isn’t, scale C1 and C3 appropriately with:
C1 = 0.5µF*10kHz/Fpwm and,
C3 = 2µF*10kHz/Fpwm.
The ensuing 5-Vpp PWM switching by Q1 creates a variable resistance averaged by C1 to R4/Df, the place Df = the 0 to 1 PWM obligation issue. Thus, at Z1’s Adj level:
Ic = 0 to 1.24V/R4 = 3.1 mA,
The second-order PWM ripple filtering provides a good 8-bit settling time of 6 ms with Fpwm = 10 kHz.
Z1 servos the V1 gate drive of Q3 to carry the FET’s supply at its precision 1.24-V reference after which degree shift the ensuing Ic to trace U1’s ADJ pin. Additionally summed with Ic is Iadj bias compensation (1.24V/20k = 62µA) offered by R2.
This time period zeros out U1’s typical Iadj and cuts its max 100 µA error by 60%. In the meantime, D1 insures that Iout is pressured to zero when 5 V drops by saturating Q2 and making Ic giant sufficient to show U1 utterly off, thus defending the load.
In regards to the 1N4001 daisy chain: There’s a risk of Iout > 0 at Ic = max and a ensuing reverse bias of the load; some hundreds may not tolerate this. The 1N4001s block that, and likewise present bias for the power-down cutoff of Iout when +5-V rail shuts down.
Be aware that the accuracy of IcRc = Vadj is assured by the match of the Rc resistors and precision of the Z1 and U1 inside references. It’s subsequently impartial of the tolerance of the +5-V rail, though it must be correct to ± 5% for finest PWM ripple suppression. Iout is linear with PWM obligation issue Df = 0 to 1:
Iout = -1.25 Df/Rs
If Rs = 1.25 Ω, then Iout(max) = 1 A.
Be aware that U1 might should dissipate as a lot as 23 W if Iout(max) = 1 A and the load voltage is low. Ethical of the story: Be beneficiant with the heatsink space! Additionally, Rs must be rated for a wattage of 1.252/Rs.
Stephen Woodward’s relationship with EDN’s DI column goes again fairly a good distance. Over 100 submissions have been accepted since his first contribution again in 1974.
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