Jane Road has launched a contest for FPGA builders, utilizing the puzzles set throughout this yr’s Introduction of Code to advertise options based mostly on synthesizable {hardware} — and entrants can win prizes as much as and together with an AMD Zynq UltraScale+ Kria KV260 FPGA growth equipment for his or her entries.
“Introduction of Code has lengthy been a favourite December ritual at Jane Road, with many collaborating within the month-long puzzle problem that encourages considerate engineering and out-of-the-box pondering — very a lot our sort of enjoyable,” Jane Road’s Benjamin Devlin explains. “Final yr, Anish, a {hardware} engineer at Jane Road, wrote about tackling your entire sequence in Hardcaml, our OCaml-based {hardware} DSL, turning these puzzles into synthesizable FPGA circuits. If you happen to missed it, his submit, Introduction of Hardcaml, walks you thru how implementing such algorithms in {hardware} grew to become a singular train in architectural design and useful resource optimization.”
Fancy an FPGA-flavored problem? Strive jane Road’s Introduction of FPGA and you may win an AMD Zynq dev board. (📷: AMD)
Now, the corporate is trying to encourage others to do the identical with the 2025 Introduction of FPGA problem. The thought: taking the programming puzzles set every year by Eric Wastl, who based the Introduction of Code problem sequence again in 2015, and fixing them in {hardware} quite than software program.
“When the ultimate AoC 2025 puzzle drops, choose any puzzles you want (no less than one and as much as as many as you need) to construct synthesizable RTL with practical I/O [Input/Output],” Devlin and Anish Singhani clarify. “Bonus factors in case you do it in Hardcaml. We’re excited to see the intelligent designs created throughout the educational and open‑supply communities, and we’d additionally like to get extra individuals attempting Hardcaml!”
Extra data on the competitors, entries for which shut on January 16, 2026, is offered on the Jane Road weblog.
