Methods to design a digital-controlled PFC, Half 1

By Jules Jackson

November 19, 2025

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Methods to design a digital-controlled PFC, Half 1

Shifting from analog to digital management

An AC/DC energy provide with enter energy larger than 75 W requires energy issue correction (PFC) to:

Take the common AC enter (90 V to 264 V) and rectify that enter to a DC voltage.
Keep the output voltage at a relentless stage (often 400 V) with a voltage management loop.
Pressure the enter present to observe the enter voltage such that the electronics load seems to be a pure resistor with a present management loop.

Designing an analog-controlled PFC is comparatively straightforward as a result of the voltage and present management loops are already constructed into the controller, making it nearly plug-and-play. The facility-supply business is at present transitioning from analog management to digital management, particularly in high-performance power-supply design. In truth, almost all newly designed energy provides in information facilities use digital management.

In comparison with analog management, digital-controlled PFC gives decrease whole harmonic distortion (THD), a greater energy issue, and better effectivity, together with built-in housekeeping capabilities.

Switching from analog management to digital management just isn’t straightforward; nevertheless, you’ll face new challenges the place steady alerts are represented in a discrete format. And in contrast to an analog controller, the MCU utilized in digital management is basically a “clean” chip; it’s essential to write firmware to implement the management algorithms.

Writing the right firmware generally is a headache for somebody who has by no means performed this earlier than. That can assist you study digital management, on this article collection, I’ll present a step-by-step information on find out how to design a digital-controlled PFC, utilizing totem-pole bridgeless PFC as a design instance for instance the benefits of digital management.

A digital-controlled PFC system

Amongst all PFC topologies, totem-pole bridgeless PFC gives the perfect effectivity. Determine 1 exhibits a typical totem-pole bridgeless PFC construction.

Determine 1 Totem-pole bridgeless PFC the place Q1 and Q2 are high-frequency switches and can work as both a PFC increase change or synchronous change primarily based on the V_AC polarity. Supply: Texas Devices

Q1 and Q2 are high-frequency switches. Based mostly on V_AC polarity, Q1 and Q2 work as a PFC increase change or synchronous change, alternatively.

At a constructive AC cycle (the place the AC line is greater than impartial), Q2 is the increase change, whereas Q1 works as a synchronous change. The heartbeat-width modulation (PWM) sign for Q1 and Q2 are complementary: Q2 is managed by D (the responsibility cycle from the management loop), whereas Q1 is managed by 1-D. This fall stays on and Q3 stays off for the entire constructive AC half cycle.

At a damaging AC cycle (the place the AC impartial is greater than line), the performance of Q1 and Q2 swaps: Q1 turns into the increase change, whereas Q2 works as a synchronous change. The PWM sign for Q1 and Q2 are nonetheless complementary, however D now controls Q1 and 1-D controls Q2. Q3 stays on and This fall stays off for the entire damaging AC half cycle.

Determine 2 exhibits a typical digital-controlled PFC system block diagram with three main operate blocks:

An ADC to sense the V_AC voltage, V_OUT voltage, and inductor present for conversion into digital alerts.
A firmware-based common current-mode controller.
A digital PWM generator.

Determine 2 Block diagram of a typical digital-controlled PFC system with three main operate blocks. Supply: Texas Devices

I’ll introduce these operate blocks one after the other.

The ADC

An ADC is the elemental aspect for an MCU; it senses an analog enter sign and converts it to a digital sign. For a 12-bit ADC with a 3.3-V reference, Equation 1 expresses the ADC outcome for a given enter sign Vin as:

Conversely, primarily based on a given ADC conversion outcome, Equation 2 expresses the corresponding analog enter sign as:

To acquire an correct measurement, the ADC sampling price should observe the Nyquist theorem, which states {that a} steady analog sign could be completely reconstructed from its samples if the sign is sampled at a price larger than twice its highest frequency element.

This minimal sampling price, often called the Nyquist price, prevents aliasing, a phenomenon the place greater frequencies seem as decrease frequencies after sampling, thus dropping details about the unique sign. Because of this, the ADC sampling price is ready at a a lot greater price (tens of kilohertz) than the AC frequency (50 or 60 Hz).

Enter AC voltage sensing

The AC enter is excessive voltage; it can’t connect with the ADC pin straight. You need to use a voltage divider, as proven in Determine 3, to cut back the AC enter magnitude.

Determine 3 Enter voltage sensing that means that you can join the excessive AC enter voltage to the ADC pin. Supply: Texas Devices

The enter sign to the ADC pin must be throughout the measurement vary of the ADC (0 V to three.3 V). However to acquire a greater signal-to-noise ratio, the enter sign must be as massive as potential. Therefore, the voltage divider for V_AC ought to observe Equation 3:

the place V_{AC_MAX}is the height worth of the utmost V_AC voltage that you simply wish to measure.

Including a small capacitor (C) with low equal collection resistance (ESR) within the voltage divider can take away any potential high-frequency noise; nevertheless, you must place C as shut as potential to the ADC pin.

Two ADCs measure the AC line and impartial voltages; subtracting the 2 readings utilizing firmware will receive the V_AC sign.

Output voltage sensing

Equally, resistor dividers will attenuate the output voltage, as proven in Determine 4, then connect with an ADC pin. Once more, including C with low ESR within the voltage divider removes any potential high-frequency noise, with C positioned as shut as potential to the ADC pin.

Determine 4 Resistor divider for output voltage sensing, the place C removes any potential high-frequency noise. Supply: Texas Devices

To totally harness the ADC measurement vary, the voltage divider for V_OUT ought to observe Equation 4:

the place V_{OUT_OVP}is the output overvoltage safety threshold.

AC present sensing

In a totem-pole bridgeless PFC, the inductor present is bidirectional, requiring a bidirectional present sensor akin to a Corridor-effect sensor. With a Corridor-effect sensor, if the sensed present is a sine wave, then the output of the Corridor-effect sensor is a sine wave with a DC offset, as proven in Determine 5.

Determine 5 The bidirectional hall-effect present sensor output is a sine wave with a DC offset when the enter is a sine wave. Supply: Texas Devices

The Corridor-effect sensor you utilize might have an output vary that’s lower than what the ADC can measure. Scaling the Corridor-effect sensor output to match the ADC measurement vary utilizing the circuit proven in Determine 6 will totally harness the ADC measurement vary.

Determine 6 Corridor-effect sensor output amplifier used to scale the Corridor-effect sensor output to match the ADC measurement vary. Supply: Texas Devices

Equation 5 expresses the amplification of the Corridor-effect sensor output:

Firmware-based common current-mode controller

As I discussed earlier, as a result of the digital controller MCU is a clean chip, it’s essential to write firmware to imitate the PFC management algorithm used within the analog controller. This consists of voltage loop implementation, present reference technology, present loop implementation, and system safety. I’ll go over these implementations in Half 2 of this text collection.

Digital compensator

In Determine 7, G_V and G_I are compensators for the voltage loop and present loop. One distinction between analog management and digital management is that in analog management, the compensator is often applied via an operational amplifier, whereas digital management makes use of a firmware-based proportional-integral-derivative (PID) compensator.

For PFC, its small-signal mannequin is a first-order system; subsequently, a proportional-integral (PI) compensator is sufficient to receive good bandwidth and part margin. Determine 7 exhibits a typical digital PI controller construction.

Determine 7 A digital PI compensator the place r(okay) is the reference, y(okay) is the suggestions sign, and Ok_p and Ok_i are positive aspects for the proportional and integral, respectively. Supply: Texas Devices

In Determine 7, r(okay) is the reference, y(okay) is the suggestions sign, and Ok_p and Ok_i are positive aspects for the proportional and integral, respectively. The compensator output, u(okay), clamps to a particular vary. The compensator additionally accommodates an anti-windup reset logic that permits the integral path to get better from saturation.

Determine 8 exhibits a C code implementation instance for this digital PI compensator.

Determine 8 C code instance for a digital PI compensator. Supply: Texas Devices

For different digital compensators akin to PID, nonlinear PID, and first-, second-, and third-order compensators, see reference [1].

S/Z area conversion

In case you have an analog compensator that works effectively, and also you wish to use the identical compensator in digital-controlled PFC, you possibly can convert it via S/Z area conversion. Assume that you’ve got a kind II compensator, as proven in Equation 6:

Exchange s with bilinear transformation (Equation 7):

the place T_s is the ADC sampling interval.

Then H(s) is transformed to H(z), as proven in Equation 8:

Rewrite Equation 8 as Equation 9:

To implement Equation 9 in a digital controller, retailer two earlier management output variables: u_n-1, u_n-2,and two earlier error histories: e_n-1, e_n-2. Then use present error e_n and Equation 9 to calculate the present management output, u_n.

Digital PWM technology

A digital controller generates a PWM sign very similar to an analog controller, with the exception {that a} clock counter generates the RAMP sign; subsequently, the PWM sign has restricted decision. The RAMP counter is configurable as up depend, down depend, or up-down depend.

Determine 9 exhibits the generated RAMP waveforms akin to training-edge modulation, rising-edge modulation, and triangular modulation.

Determine 9 Generated RAMP waveforms akin to training-edge modulation, rising-edge modulation, and triangular modulation. Supply: Texas Devices

Programming the PERIOD resistor of the PWM generator will decide the switching frequency. For up-count and down-count mode, Equation 10 calculates the PERIOD register worth as:

the place f_clk is the counter clock frequency and f_sw is the specified switching frequency.

For the up-down depend mode, Equation 11 calculates the PERIOD register worth as:

Determine 10 exhibits an instance of utilizing training-edge modulation to generate two complementary PWM waveforms for totem-pole bridgeless PFC.

Determine 10 Utilizing training-edge modulation to generate two complementary PWM waveforms for totem-pole bridgeless PFC. Supply: Texas Devices

Equation 12 exhibits that the COMP equals the present loop G_I output multiplied by the switching interval:

The upper the COMP worth, the larger the D.

To forestall quick via between the highest change and the underside change, including a delay on the rising fringe of PWMA and the rising fringe of PWMB inserts lifeless time between PWMA and PWMB. This delay is programmable, which implies that it’s potential to dynamically alter the lifeless time to optimize efficiency.

Blocks in digital-controlled PFC

Now that you’ve got discovered concerning the blocks utilized in digital-controlled PFC, it’s time to shut the management loop. Within the subsequent installment, I’ll talk about find out how to write firmware to implement a median current-mode controller.

Bosheng Solar is a system engineer and Senior Member Technical Employees at Texas Devices, centered on growing digitally managed high-performance AC/DC options for server and business purposes. Bosheng obtained a Grasp of Science diploma from Cleveland State College, Ohio, USA, in 2003 and a Bachelor of Science diploma from Tsinghua College in Beijing in 1995, each in electrical engineering. He has printed over 30 papers and holds six U.S. patents.