Location: Bengaluru
Firm: ARM
Tasks
Architect, implement, and validate revolutionary DFT methods on test-chips and hard-macros. Insert DFT logic into SoC-style designs on the RTL stage and on the Synthesis gate stage, validate all options, and generate ATE-targeted check patterns to be run on silicon. Work intently with front-end design and verification groups on DFT RTL stage insertion, back-end synthesis, place-and-route, and static-timing-analysis groups on DFT gate stage insertion and timing closure, and Take a look at and Debug groups on silicon characterization and validation.
Required Expertise and Expertise
- This position is for a Senior DFT Engineer with 4+ years of confirmed expertise in Design for Take a look at
- Expertise coding in Verilog RTL, and scripting language like TCL, and/or Perl
- Proficient in Unix/Linux environments
- Core DFT expertise thought of essential for this place ought to embrace a few of the following: Scan compression and insertion, Reminiscence BIST, Logic BIST, JTAG/IJTAG, at-speed check, ATPG, fault simulation, back-annotated gate-level verification, silicon debug
- Expertise with Siemens, Cadence, and/or Synopsys DFT and simulation instruments
“Good To Have” Expertise and Expertise
- Familiarity with IEEE 1149, 1500, 1687
- Familiarity with Synthesis and Static Timing Evaluation
- Working data of Siemens DFT instruments
- Capability to work each collaboratively on a crew and independently.
- Modern and a ardour for progress
- Laborious-working and glorious time administration expertise with a capability to multi-task
