I designed the circuit in Determine 1 as part of an information transmission system that has a provider frequency of 400 kHz utilizing on-off keying (OOK) modulation.

I wanted to detect the presence of the provider by distinguishing it from different alerts of various frequencies. It was transformed to digital with a 5-V logic. I needed to keep away from utilizing programmable units and timers based mostly on RC circuits.

Wow the engineering world along with your distinctive design: Design Concepts Submission Information

The ensuing circuit is made up of 4 chips, together with a crystal time base. Briefly, this technique measures the time between the rising edges of the obtained sign on a cycle-by-cycle foundation. Thus, it detects if the incoming sign is legitimate or not in a short while (roughly one provider cycle, that’s ~2.5 µs). That is finished independently of the sign responsibility cycle and in much less time than different programs, equivalent to a phase-locked loop (PLL), which can take a number of cycles to detect a frequency.

Determine 1 A digital frequency divider circuit that detects the presence of a 400-kHz provider, distinguishing it from alerts of different frequencies, after it has been transformed to digital utilizing 5-V logic.

The way it works

Within the schematic, IC1A and IC1B are the 6.144 MHz crystal oscillator and a buffer, respectively. For X1, I used an ordinary quartz crystal salvaged from an previous microprocessor board.

The flip-flops IC2A and IC2B are interconnected such {that a} rising edge on the IC2A clock enter (linked to the sign enter) produces, by its output and IC2B enter, a low logic degree at IC2B Q output. Instantly afterwards, the low logic degree resets IC2A, thereby leaving IC2B able to obtain a rising edge at its clock enter, which causes its Q output to return to excessive once more. For the reason that IC2B clock enter is constantly receiving the 6.144 MHz clock, the low logic degree at its output could have a really quick period. That very slim pulse presets IC3, which takes its counting outputs to “0000”.

If IC4A is in a reset situation, that pulse will even set it in the way in which defined beneath, with the impact of releasing IC4B by deactivating its enter (pin 4 of IC4) and enabling IC3 by pulling its enter low.

From that prompt, IC3 will rely the 6.144 MHz pulses, and, if the following rising fringe of the enter sign happens when IC3’s rely is at “1110” or “1111”, IC1C’s output can be at a low degree, so the IC4B output will go excessive, indicating {that a} cycle with concerning the appropriate interval (2.5µs) has been obtained. Concurrently, IC3 can be preset to begin a brand new rely. If the following rising edge occurred when the IC3 rely was not but at “1110”, IC3 would nonetheless be preset, however the circuit output would go low. This final state of affairs corresponds to an enter frequency increased than 400 kHz.

Quite the opposite, if, after the final rising edge, an extended time than a legitimate interval passes, the functioning of the circuit would be the following. When the IC3 rely reaches the worth “1111”, a 6.144 MHz clock pulse will happen on the sign enter as an alternative of a rising edge. It will make the IC4A Q output take the low degree current on the IC3 output and the IC4A information enter.

The low degree at IC4A Q output will set IC4B, and the circuit output will go low. As IC4A Q output can also be linked to its personal enter, that low degree attributable to a pulse at its clock enter will stop that flip-flop from responding to additional clock pulses. From then on, the one means of taking IC4A out of that state can be by making use of a low degree (could possibly be a really slim pulse, as on this case) at its enter (pin 10 of IC4). That might set up a forbidden situation for an prompt, making IC4A first pull excessive each Q and , and instantly change to low.

Because of the circuit logic and timing, after a whole cycle with a interval of roughly 2.5 µs is obtained, the circuit output goes excessive and stays in that state till a shorter cycle is obtained, or till an extended time than the right interval elapses with no full cycle.

Testing the circuit

I examined the circuit with alerts from 0 to 10 MHz. The frequencies between 384 kHz and 405 kHz, or intervals between 2.47 µs and a pair of.6 µs, produced a excessive degree on the output. These values correspond to roughly 15 to 16 pulses of the 6.144 MHz clock, being the primary of these pulses used to finish the presetting of the counter IC3, so it isn’t counted.

Frequencies decrease than 362 kHz or increased than 433 kHz produced a low logic degree. For frequencies between 362 kHz and 384 kHz and between 405 kHz and 433 kHz, the circuit produced pulses on the output. That implies that for an enter interval between 2.31 µs and a pair of.47 µs or between 2.60 µs and a pair of.76 µs, there can be some chance that the output can be in a excessive or low logic state. That state will depend upon the section distinction between the enter sign and the 6.144 MHz clock.

Determine 2 reveals a five-pulse 400 kHz burst (decrease hint), which is utilized to the enter of the circuit. The higher hint is the output; it may be seen that after the primary cycle has been measured. The output goes excessive, and it stays in that state as extra 2.5 µs cycles maintain arriving. After a time barely increased than 2.5 µs with no full cycle (~2.76 µs), the output goes low.

Determine 2 A five-pulse 400-kHz burst utilized to the enter of the digital frequency divider circuit (CH2) and the output (CH2) after the primary cycle has been measured.

Ariel Benvenuto is an Electronics Engineer and a PhD in physics, and works in analysis with IFIS Litoral in Santa Fe, Argentina.

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