Working from DC to three.1 GHz, the SKY53510, SKY53580, and SKY53540 clock buffers from Skyworks present 10, 8, and 4 outputs, respectively. These low-jitter units help high-speed communication infrastructure, together with information facilities, 5G networks, and PCIe 7.0.
Every machine integrates a 3:1 enter multiplexer that accepts two common inputs—suitable with LVPECL, LVDS, S-LVDS, HCSL, CML, SSTL, and HSTL—in addition to a crystal enter (additionally usable with a single-ended clock). The inputs help slew charges right down to 0.75 V/ns. Differential outputs are organized in two banks, with every financial institution independently selectable as LVPECL, LVDS, HCSL, or tristate and powered by its personal 1.8-V, 2.5-V, or 3.3-V provide.
The buffers obtain low additive jitter, specified at 35 fs typical (47 fs max) at 156.25 MHz and three fs at 100 MHz for PCIe 7. A number of on-chip LDO regulators present >70 dBc PSRR in noisy environments, whereas a -166 dBc/Hz noise flooring permits operation with Synchronous Ethernet (SyncE) at 156.25 MHz.
Samples and manufacturing portions of the SKY53510/80/40 clock buffers can be found now.
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