In telecommunication functions, goal impedance serves as an important benchmark for energy distribution community (PDN) design. It ensures that the die operates inside an appropriate stage of rail voltage noise, even below the worst-case transient present eventualities, by defining the utmost allowable PDN impedance for the facility rail on the die.
This text will concentrate on the optimization strategies to satisfy the goal impedance utilizing a point-of-load (PoL) machine, whereas offering invaluable insights and sensible steerage for designers looking for to optimize their PDNs for dependable and environment friendly energy supply.
Defining goal impedance
With the rise of high-frequency indicators and escalating energy calls for on boards, energy designers are prioritizing noise-free energy distribution that may effectively provide energy to the IC. Controlling the facility supply community’s impedance throughout a sure frequency vary is one method to ensure correct operation of high-speed techniques and meet efficiency calls for.
This impedance can typically be estimated by dividing the utmost allowed ripple voltage by the utmost anticipated present step load. The facility supply community’s goal impedance (ZTARGET) might be calculated with beneath equation:
Reaching ZTARGET throughout a large frequency spectrum requires an influence provide at decrease frequencies, mixed with strategically positioned decoupling capacitors at center and better frequencies. Determine 1 reveals the impedance frequency traits of multi-layer ceramic capacitors (MLCCs).
Determine 1 The impedance frequency traits of MLCCs are proven throughout a large frequency spectrum. Supply: Monolithic Energy Techniques
Sustaining the impedance beneath the calculated threshold ensures that even essentially the most extreme transient currents generated by the IC, in addition to induced voltage noise, stay inside acceptable operational boundaries.
Determine 2 reveals the various goal impedance throughout completely different frequency ranges, based mostly on knowledge from Qualcomm web site. This implies each ingredient within the energy distribution have to be optimized at completely different frequencies.
Determine 2 Here’s a goal impedance instance for various frequency ranges. Supply: Qualcomm
Understanding PDN impedance
In idea, an influence rail goals for the bottom attainable PDN impedance. Nonetheless, it’s unrealistic to attain a great zero-impedance state. A extensively adopted technique to reduce PDN impedance is putting varied decoupling capacitors beneath the system-on-chip (SoC), which flattens the PDN impedance throughout all frequencies. This prevents voltage fluctuations and sign jitter on output indicators, but it surely’s not essentially the simplest methodology to optimize energy rail design.
Three-stage low-pass filter method
To additional discover optimizing energy rail design, the basics of PDN design have to be re-examined along with contemplating new approaches to attain optimum efficiency. Determine 3 reveals the PDN conceptualized as a three-stage low-pass filter, the place every stage of this community performs a selected position in filtering and stabilizing the present drawn from the SoC die.
Determine 3 The PDN is conceptualized as a three-stage low-pass filter. Supply: Monolithic Energy Techniques
The three-stage low-pass filter is described beneath:
- Present drawn from the SoC die: The method begins with present being drawn from the SoC die. Any present drawn is filtered by the package deal, which interacts with die-side capacitors (DSCs). This preliminary filtering stage reduces the present’s slew fee earlier than it reaches the PCB socket.
- PCB structure issues and MLCCs: As soon as the present passes by means of the PCB ball grid arrays (BGAs), the second stage of filtering happens as the present flows by means of the facility planes on the PCB and encounters the MLCCs. Throughout this stage, it’s essential to concentrate on deciding on capacitors that successfully function at particular frequencies. Excessive-frequency capacitors positioned beneath the SoC don’t considerably affect decrease frequency regulation.
- Voltage regulator (VR) with energy planes and bulk capacitors: The ultimate stage entails the VR and bulk capacitors, which work collectively to stabilize the facility provide by addressing lower-frequency noise.
The PDN’s three-stage method ensures that every element contributes to minimizing impedance throughout completely different frequency bands. This structured methodology is important for reaching dependable and environment friendly energy supply in trendy digital techniques.
Case examine: Telecom analysis board evaluation
This in-depth examination makes use of a telecommunications-specific analysis board from MPS, which demonstrates the capabilities of the MPQ8785, a high-frequency, synchronous buck converter, in a real-world setting. Furthermore, this case examine underlines the significance of capacitor choice and placement to satisfy the goal impedance.
To provoke the method, PCB parasitic extraction is carried out on the MPS analysis board. Determine 4 reveals a prime view of the MPQ8785 analysis board structure, the place two ports are chosen for evaluation. Port 1 is positioned after the inductor, whereas Port 2 is linked to the SoC BGA.
Determine 4 PCB parasitic extraction is carried out on the telecom analysis board. Supply: Monolithic Energy Techniques
Capacitor fashions from vendor web sites are additionally included on this structure, together with the equal sequence inductance (ESL) and equal sequence resistance (ESR) parasitics. As many capacitor fashions as attainable are allotted beneath the SoC within the backside of the PCB to take care of a flat impedance profile.
Desk 1 Right here is the preliminary capacitor choice for various portions of capacitors focusing on completely different frequencies. Supply: Monolithic Energy Techniques
Determine 5 reveals a comparability of the goal impedance profile outlined by the PDN masks for the core rails to the precise preliminary impedance measured on the MPQ8785 analysis board utilizing the initially chosen capacitors. This graphical comparability permits a direct evaluation of the impedance traits, facilitating the analysis of the PDN efficiency.
Determine 5 Here’s a comparability between the goal impedance profile and preliminary impedance utilizing the initially chosen capacitors. Supply: Monolithic Energy Techniques
Based mostly on the information from Determine 5, the impedance exceeds the desired restrict inside the 300-kHz to 600-kHz frequency vary, indicating that further capacitance is required to mitigate this difficulty. Introducing further capacitors successfully reduces the impedance on this frequency band, guaranteeing compliance with the specification.
Notably, high-frequency capacitors are additionally noticed to have a negligible influence on the impedance at greater frequencies, suggesting that their contribution is proscribed to particular frequency ranges. This perception informs optimizing capacitor choice to attain the specified impedance profile.
By means of an in depth sequence of simulations that systematically consider varied capacitor configurations, the optimum mixture of capacitors required to fulfill the impedance masks necessities was efficiently recognized.
Desk 2 The outcomes of this iterative course of define the optimum amount of capacitors and whole capacitance. Supply: Monolithic Energy Techniques
The ultimate capacitor choice ensures that the PDN impedance profile meets the desired masks, thereby guaranteeing dependable energy supply and efficiency. Determine 6 reveals the ultimate impedance with optimized capacitance.
Determine 6 The ultimate impedance with optimized capacitance meets the desired masks. Supply: Monolithic Energy Techniques
With a adequate margin at frequencies above 10 MHz, capacitors that primarily have an effect on greater frequencies might be eradicated. This strategic discount minimizes the occupied space and reduces prices whereas sustaining compliance with all specs. Efficiency, value, and area issues are successfully balanced through the use of the optimum mixture of capacitors required to fulfill the impedance masks necessities, enabling strong PDN performance throughout the operational frequency vary.
To facilitate the case examine, the impedance masks was modified inside the 10-MHz to 40-MHz frequency vary, lowering its total worth to 10 mΩ. Implementing 10 further 0.1-µF capacitors was useful to cut back impedance within the analysis board, which then successfully lowered the impedance within the frequency vary of curiosity.
Determine 7 reveals the decreased impedance masks in addition to the analysis board’s impedance response. The added capacitance efficiently reduces the impedance inside the specified frequency vary.
Determine 7 The decreased PDN masks with optimized capacitance reduces impedance inside the specified frequency vary. Supply: Monolithic Energy Techniques
Compliance with impedance masks
This text used the MPQ8785 analysis board to optimize PDN efficiency, guaranteeing compliance with the desired impedance masks. By means of this optimization course of, fashions have been developed to foretell the influence of varied capacitor sorts on impedance throughout completely different frequencies, which facilitates the number of appropriate parts.
Capacitor choice for optimized energy rail design is dependent upon the precise impedance masks and frequency vary of curiosity. A random number of capacitors for all kinds of frequencies is inadequate for optimizing PDN efficiency. Moreover, the bodily structure should reduce parasitic results that affect total impedance traits, the place particular consideration have to be given to optimizing the structure of capacitors to mitigate these results.
Marisol Cabrera is utility engineer manger at Monolithic Energy Techniques (MPS).
Albert Arnau is utility engineer at Monolithic Energy Techniques (MPS).
Robert Torrent is utility engineer at Monolithic Energy Techniques (MPS).
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