We’ve seen numerous fascinating conversations and Design Thought (DI) collaboration devising circuits for energy switching utilizing cheap (and cute!) momentary-contact SPST pushbuttons. A latest and fascinating extension of this theme by frequent contributor R Jayapal addresses management of comparatively excessive DC voltages: 48 volts in his chosen case.
Wow the engineering world together with your distinctive design: Design Concepts Submission Information
In the middle of implementing its excessive voltage characteristic, Jayapal’s design switches the damaging (Vss a.ok.a. “floor”) rail of the incoming provide as an alternative of the (extra standard) optimistic (Vdd) rail. After all, there’s completely nothing bodily incorrect with this selection (definitely the electrons don’t know the distinction!). However as a result of it’s a bit unconventional, I fear that it’d create prospects for the unwary to make unintentional, and probably damaging, misconnections.
Determine 1’s circuit takes a distinct tack to keep away from that.
Determine 1 Flip ON/Flop OFF referenced to the V+ rail. If V+ < 15v, then set R4 = 0 and omit C2 and Z1. Be certain that C2’s voltage ranking is > (V+ – 15v) and if V+ > 80v, R4 > 4V+2
Determine 1 returns to an earlier theme of utilizing a PFET to change the optimistic rail for energy management, and a pair of unbuffered CMOS inverters to create a toggling latch to manage the FET. The fundamental circuit is described in “Flip ON Flop OFF with no Flip/Flop.”
What’s completely different right here is that every one circuit nodes are referenced to V+ as an alternative of floor, and Zener Z1 is used to synthesize an area bias reference. Consequently, any V+ rail as much as the restrict of Q1’s Vds ranking could be accommodated. After all, if even that’s not adequate, greater rated FETs can be found.
You’ll want to tie the inputs of any unused U1 gates to V+.
Stephen Woodward’s relationship with EDN’s DI column goes again fairly a good distance. Over 100 submissions have been accepted since his first contribution again in 1974.
Associated Content material
- Flip ON flop OFF
- Flip ON Flop OFF for 48-VDC programs
- Flip ON Flop OFF with no Flip/Flop
- Embellishments of yet one more Flip-On Flop-Off circuit
- Latching D-type CMOS energy change: A “Flip ON Flop OFF” different
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