Implementing a easy digital-to-analog converter (DAC) by cascading a single pulse width modulator (PWM) and an analog low-pass filter is nothing new. Neither is making use of to a filter the sum of the outputs of a most important 2N-count PWM and a least vital 2N-count one to get a composite 22N-bit DAC [1][2]. However designing one with easy, adjustment-free topologies and fairly correct, repeatable efficiency traits is just not trivial. A proposed instance is seen in Determine 1. Let’s look at the circuit from the output to the enter.
Determine 1 The PWM—pushed 16-bit DAC. Capacitors C1, C2, and C3 are NPO/COG ceramic.
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Op amp
The OPA383 is a “rail-to-rail” enter and output op amp. Typical of such components, the output doesn’t fairly swing to the rails. A detailed take a look at the spec reveals that the V+ and V- provides ought to be a minimum of ±155 mV past the vary of output alerts, and their distinction ought to be lower than 5.5 V. Enter offset voltage is ±5 µV most at 25°C, however sadly, we’re not given limits over temperature. Nonetheless, a graph of 5 measured models exhibits restricted susceptibility to temperature. Let’s assume thrice 5, or a 15 µV most over the temperature vary.
The bias present is ±76 pA most from -40°C to +85°C. I’d wish to maintain the design’s varied unbiased error contributions beneath ½ PWM rely (on this case, beneath 2-17 of full-scale). Contemplating the beneath 100 kΩ resistance seen by the op amp enter, full-scale DAC voltages over 2.0 V would encounter errors lower than ½ rely on account of bias present and offset voltage.
The op amp’s DC acquire is a minimal of 118 dB, and its gain-bandwidth (GBW) product is 2.5 MHz typical. Within the absence of different data, I’ll assume and work with a minimal GBW of 1 MHz.
PWM filter
The filter consists of U2, Ra, Rb1, Rb2, R1, R2, R3, C1, C2, and C3. It’s essential to maintain a deal with on the tolerances of those passive elements to make sure repeatable outcomes. The capacitances of widespread ceramic varieties akin to Y5V and X7R are very delicate to temperature and to DC voltage; they don’t seem to be really helpful to be used in filters requiring any vital stability. Movie and ceramic COG/NPO varieties are far much less delicate. NPO/COG capacitors and the resistors of the values and tolerances proven within the schematic can be found for effectively beneath $0.10 in 1000-piece portions.
The filter proven is a 3rd-order one (evident from the presence of three capacitors). Usually, 3rd-order filters supply a smaller (higher) product of settling time and ripple attenuation issue than 2nd-order filters (two capacitors). Design aids for 3rd-order varieties are uncommon, so I’ve used one I developed and revealed in EDN virtually 15 years in the past [3]. This filter doesn’t depend on the cancellation of huge alerts of opposing phases, so there is no such thing as a want for adjustment pots to cope with the dearth of zero-tolerance elements that may in any other case be required to attain maximal nulling.
It’s the job of the filter to suppress the AC “ripple” of PWM alerts, that are at their worst when the output is 50% of full scale. Minimization of settling time can also be of curiosity. To evaluate the results of variations on account of part tolerances, Determine 2 and Determine 3 present 100-run Monte Carlo trials of settling occasions for a zero to full-scale transition and for ripple attenuation.
Determine 2 100 Monte Carlo runs of a transition from 0 to full scale, 0 to 65535 counts. Settling to higher than ½ rely happens in lower than 2 milliseconds.
Determine 3 100 Monte Carlo runs of ripple, the place full scale is 65535 counts. Ripple is lower than ½ PWM rely peak and 1 rely peak-to-peak. PWM frequency is 78 kHz.
Summing community
There are two 8-bit PWMs. To create a 16-bit sign, the contribution of essentially the most vital PWM sign is weighted by an element very near 256 occasions bigger than that of the much less vital PWM sign. A summing community of Ra and Rb1 + Rb2 accomplishes this. (Be aware that the remaining filter elements don’t have any DC impact on this community.)
Filter drivers (logic Inverters)
The logic inverters proven driving the summing community have finite output resistances, which successfully add to these of Ra and R1b. Sadly, logic inverters will not be linear gadgets and will not be characterised as such. One of the best ways to find out most output resistance from their information sheets is to first establish the required provide voltage nearest (however lower than or equal) to the one supposed to be used, after which divide the utmost output voltage drop by the required load present.
It’s finest to do that for the excessive facet, as its resistance is usually increased than that of the low facet. As an illustration, if a 3.3-V provide is meant for a Texas Devices SN74AC04, use the datasheet’s 2.46-V minimal for a 3-V provide drawing 12 mA to reach at a most resistance of 45 Ω. Paralleling 5 gates will scale back that resistance to an unknown quantity beneath 9 Ω. The quantity is unknown as a result of the person inverters share widespread resistances on the wafer and within the wafer-to-package bonding wires. And so as much as 9 Ω is added to Ra. The as much as 45 Ω added to Rb has a comparably negligible impact.
However right here we depart from the objective of limiting an error supply to a most contribution of ½ rely—the utmost differential non-linear error is now just below 1 rely. Happily, even with this error, an rising sequence of counts yields a monotonically rising sequence of output voltages. If the efficiency enchancment is price the fee, you can keep beneath a ½ rely error by doing the next:
- Changing the inverter with the low-resistance, dual-channel TS5A22362DRCR analog swap
- Changing the R1a1% half with a 0.05% half
- Changing the 30.1 kΩ R1b with a 28.7 kΩ 1% resistor in sequence with a 5% 510-Ω unit.
Driver energy provide
Alas, as soon as once more, we should abandon the objective of preserving the errors launched to lower than ½ LSb. The TI REF35 IC’s ±0.05% at 25°C score equates to 33 LSb’s! And even with the advantage of calibration and added {hardware} to regulate the inverter/analog swap’s provide voltage, the reference’s 12 ppm/°C temperature variations would depart us within the lurch. As soon as once more, we now have to eat some error.
Within the spirit of continuous to do our greatest with the playing cards dealt, the reference’s DC resistance (60 ppm max of three.3 V (for example) / 1 mA) is about solely 0.2 Ω. That is negligible when met with the DC resistance seen by the summing community of Ra and Rb. Transients from the inverters are a priority, nevertheless.
Ample decoupling of these gadgets is a should. Moreover, the AC impedance as a result of mixture of R1, Ra Rb, and C1 of roughly Zsum = 16.5 kΩ seems on the inverter outputs and so additionally throughout their provide terminals. Happily, these are at frequencies no decrease than the PWM frequency (see subsequent part for this worth). The capacitors proven maintain the impedance at this frequency effectively beneath 0.1% of the just about utterly resistive Zsum. For sensible concerns, the magnitude of this mixture is indistinguishable from that of Zsum.
PWM sign supply
The PWM sign supply might be a microprocessor. Lately, most of them will be clocked at 20 MHz or larger, that means that they might all supply 8-bit PWMs of a minimum of 20 MHz / 256 = 78 kHz. It’s this frequency or increased that the filter was designed for. So why not use microprocessor GPIO PWM outputs as drivers?
First, there’s the often pretty excessive GPIO output resistance. Moreover, should you’ve ever seemed carefully on the voltage of a microprocessor digital output, you may need seen that it’s just a few millivolts and even tens of millivolts from floor and the system’s provide. It’s because the processor is performing capabilities along with producing a PWM, which draw vital present, producing voltage drops by parts of the IC wafer and its package deal bonding wires. The SN74AC74 has no such different capabilities, and any such voltage drops are a part of the voltage drop specs mentioned earlier.
Modifications
Need decrease ripple amplitude? Enhance the PWMs’ frequency. Need quicker settling time? The resistance trying into Ra and Rb is Rab = 4009 Ω. Cut back R3, R2, and R1—Rab by some issue and/or C1, C2, and C3 by the identical or completely different issue. Enhance the PWMs’ frequency by a minimum of the product of the elements. Enhance it additional to attain each enhancements.
To sum it up
A easy design has been launched for a PWM-driven 16-bit DAC. Peak ripple is lower than ½ LSb and the circuit settles to this stage in lower than 2 ms. Monte Carlo analyses present that these parameters are met even contemplating passive part and op amp GBW tolerances. In 1k portions, the reference is about $1, the op amp is beneath $0.75, and the filter passives are every beneath $0.10.
Error sources in varied components of the circuit have been recognized and, the place potential, restricted to not more than ½ LSb. To deal with different bigger errors, strategies of further {hardware} and calibration have been made, however the temperature sensitivity of the voltage reference is a limiting issue.
Christopher Paul has labored in varied engineering positions within the communications trade for over 40 years.
Associated Content material/References
- Double up on and ease the filtering necessities for PWMs
- Inherently DC correct 16-bit PWM TBH DAC
- Design second- and third-order Sallen-Key filters with one op amp
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