Location: Pune
Firm: Lattice Semiconductor
Duties & Expertise
Lattice Semiconductor is searching for a SoC RTL Design Engineer to hitch the HW design group targeted on IP design and full chip integration. This place is a chance to be a part of a dynamic group with ample alternative to contribute, be taught, innovate and develop.
Function Specifics
- It is a full-time particular person contributor place positioned in Pune, India.
- The position will give attention to RTL design and full chip integration and initiatives concentrated in Pune and related time zones.
- The certified candidate might be working in RTL design, best-in-class coding kinds, algorithms, and each Verilog and System Verilog.
- The certified candidate might be working in SoC integration and related high quality checks together with lint, CDC, RDC, SDC and many others.
- The position requires to work with architect and micro-architect group to grasp outline design specs
- The profitable candidate might be open and prepared to each (a) educate best-known-methods to an current design group and (b) be taught from the group concerning the issues of extremely programmable FPGA materials. This position carries the should be each a robust educator and an open-minded pupil.
Accountabilities
- Function a key contributor to RTL design efforts.
- Drive logic design of key blocks & full chip and convey best-in-class methodologies to speed up design time and enhance design high quality.
- Making certain design high quality by way of assertions, checkers, and scripting.
- Develop robust relationships with worldwide groups.
- Mentor and develop robust companions and colleagues.
- Occasional journey as wanted.
Required Expertise
- BS/MS/PhD Electronics Engineering, Electrical Engineering, Pc Science or equal.
- 5+ years of expertise in driving logic design throughout a large number of silicon initiatives.
- Experience in SoC integration, defining micro-architecture and expertise of choosing third occasion IP.
- Expertise in working with ARM processor, AXI, AMBA bus, ENET, PCIE, security and safety protocols, debug structure might be plus.
- Familiarity with FPGA designs, use-cases, and design issues is a plus.
- Impartial employee and chief with demonstrated problem-solving talents.
- Confirmed potential to work with a number of teams throughout completely different websites and time zones.
