Integrating ADCs that present correct outcomes with out requiring a precision integrator capacitor has been round for a very long time. A venerable instance is that multimeter favourite, the dual-slope ADC. That traditional topology makes use of only one integrator to alternately accumulate each incoming sign and complementary voltage references with the identical RC time fixed. It thus routinely ratios out time fixed tolerance. Slick.
This Design Thought (DI) will describe a (probably) new integrating converter that reaches an identical objective of correct conversions without having an correct capacitor. But it surely will get there through a considerably completely different route. Alongside the route, it picks up some advantageous wrinkles.
Wow the engineering world along with your distinctive design: Design Concepts Submission Information
As Determine 1 exhibits, the design begins off with an outdated buddy, the 555-analog timer.
Determine 1 Op-amp A1 constantly integrates the incoming Vin sign, thus minimizing noise. Conversion happens in alternating phases, T- and T+. The T-/T+ part period ratio is impartial of the RC time fixed, is subsequently insensitive to C1 tolerance, and incorporates each Vin magnitude and polarity info.
Incoming sign Vin is summed with the voltage at node X and collected by differential integrator A1. A conversion cycle begins when A1’s output (node Y) reaches 4.096 V and lifts timer U1’s threshold pin (Thr) by way of the R2/R3 divider to the two.048-V reference provided by voltage reference Z1. This switches on U1’s Dch pin, grounding A1’s noninverting enter by way of the R4/R5 divider, outputs a zero to the GPIO bit (node Z), and begins the T- part as A1’s output ramps down. The period of this T- part is given by:
T- = R1C1/(1 + Vin/Vfullscale)
Vfullscale = ±2.048v(R1/R6) = ±0.683v
The T- part ends when A1’s output reaches U1’s set off (Trg) voltage set to 1.024 V by Z1 and U1’s inside 2:1 divider. See the LMC555 datasheet for the gritty particulars.
This begins the T+ conversion part with an output of 1 on the GPIO bit, and the discharge of Dch by U1, which drives A1’s noninverting enter to 1.024 V, set by Z1 and the R4/R5 divider. The T+ positive-going ramp continues till A1’s output reaches the 4.096 VThr threshold described above and initiates the following conversion cycle.
T+ part period is:
T+ = R1C1/(1 – Vin/Vfullscale)
This frenetic frenzy of exercise is summarized in Determine 2.
Determine 2 Numerous conversion indicators discovered at circuit nodes X, Y, and Z.
In the meantime, the GPIO pin is assumed to be related to an acceptable microcontroller counter/time peripheral that’s accumulating T- and T+ durations for a selected decision and conversion fee. One thing between 1 µs and 100 ns ought to work for the following Vin calculation. This brings up that declare of immunity to integrator capacitor tolerance you may be questioning about.
The durations of the T+ and T- ramps are proportional to C1, as proven in Determine 3.
Determine 3 Black = Vin, Pink = T+ period in ms, Blue = T- period, C1 = 0.001 µF.
Nonetheless, software program arithmetic saves the day (and perhaps even my repute!) as a result of restoration of Vin from the uncooked part period timeouts includes a little bit of divide-and-conquer.
Vin = Vfullscale ((1 – (T-/T+))/(1 + (T-/T+)))
And, in fact, when T- is split by T+, the R1C1 phrases conveniently disappear, taking sensitivity to C1 tolerance away with them!
A last phrase about Vfullscale. The ±0.683 V determine derived above is a minimal worth, however any bigger span will be simply accommodated by including one resistor (R8) and altering one other (R1). Right here’s the scale-changing arithmetic:
R1 = 1M * Vfullscale/0.683
R8 = 1/(1/1M – 1/R1)
For instance, ±10 V is illustrated in Determine 4.
Determine 4 A ±10-V Vin span is well accommodated – if you could find a 15 MΩ precision resistor.
Word that R1 would in all probability should be a sequence string to get to fifteen MΩ utilizing OTS resistors.
Stephen Woodward’s relationship with EDN’s DI column goes again fairly a great distance. Over 100 submissions have been accepted since his first contribution again in 1974.
Associated Content material
- 15-bit voltage-to-time ADC for “Correct Perform” anemometer linearization
- Inductor-based astable 555 timer circuit
- Gated 555 astable hits the bottom working
- EDN Entry–05.08.97 Digital place encoder does away with ADC
- Including one resistor improves anemometer analog linearity to higher than +/-0.5%
- Voltage-to-period converter improves pace, price, and linearity of A-D conversion
The submit One other bizarre 555 ADC appeared first on EDN.
