Location: Bengaluru
Firm: Intel
Job Description
Develops the logic design, register switch degree (RTL) coding, and simulation for blended sign and/or highspeed IPs required to generate cell libraries, purposeful items, IP blocks, and subsystems for integration in full chip designs. Participates within the definition of structure and microarchitecture options of the block being designed. Applies varied methods, instruments, and strategies for blended sign designs together with analog habits modeling and circuit simulation to jot down RTL and optimize blended sign logic to qualify the design to satisfy energy, efficiency, space, and timing objectives in addition to design integrity for bodily implementation. Opinions the verification plan and implementation to make sure design options are verified appropriately and resolves and implements corrective measures for failing RTL checks to make sure correctness of options. Helps SoC clients to make sure highquality integration of the IP block.
{Qualifications}:
MS/MTech with 3-8 years of expertise
