Cadence taped out an LPDDR6/5X reminiscence IP system working at 14.4 Gbps—as much as 50% sooner than previous-generation LPDDR DRAM. The whole PHY and controller system optimizes energy, efficiency, and space, whereas supporting each LPDDR6 and LPDDR5X protocols. Cadence expects the IP to assist AI infrastructure meet the reminiscence bandwidth and capability calls for of huge language fashions (LLMs), agentic AI, and different compute-heavy workloads.
The reminiscence system contains a scalable, adaptable structure that pulls on Cadence’s DDR5 (12.8 Gbps), LPDDR5X (10.7 Gbps), and GDDR7 (36 Gbps) IP strains. As the primary providing within the LPDDR6 IP portfolio, it helps native integration into monolithic SoCs and permits heterogeneous chiplet integration via the Cadence chiplet framework for multi-die system designs.
Customizable for varied package deal and system topologies, the LPDDR6/5X PHY is obtainable as a drop-in hardened macro. The LPDDR6/5X controller, offered as a mushy RTL macro, features a full set of industry-standard and superior reminiscence interface options, equivalent to help for the Arm AMBA AXI bus.
The LPDDR6/5X reminiscence IP system is now accessible buyer engagements.
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