System-level check (SLT), as soon as used largely as a stopgap measure to catch points missed by automated check tools (ATE), has developed right into a vital check insertion for high-performance processors, chiplets, and different superior computational gadgets. Right now, SLT is crucial for making certain that chips perform appropriately in real-world circumstances, and all main CPUs, APUs, and GPUs now undergo an SLT insertion earlier than cargo.
Including SLT in manufacturing is being thought of for community processors and automotive processors for driver help. Nonetheless, implementing SLT strategies successfully at scale poses key challenges when it comes to managing prices, check occasions, and producers’ expectations.
One of many greatest misconceptions about SLT is that it features like ATE. ATE primarily makes use of pre-defined check patterns to stimulate circuit paths and verify anticipated responses inside particular person cores or circuit blocks. Alternatively, SLT focuses on system interactions that happen between these cores or outdoors the chip.
That features software program, energy administration, sensor integration, and communication between inner cores and peripheral gadgets. Since SLT is usually used to check cutting-edge chips, the check setting must be versatile in order that it might probably deal with application-specific circumstances and completely different interface protocols.
This distinction is especially related because the business shifts towards chiplet-based architectures. With chiplets, producers want to check how indicators propagate throughout a number of interconnected dies, relatively than simply validating particular person parts in isolation.
Take a look at sample creation for conventional ATE strategies, used for chip package-level testing, presents restricted entry to inner interactions inside a multi-chip package deal. SLT, however, can train how knowledge flows between chiplets and the way this influences efficiency, energy consumption, and general system performance.
Nonetheless, this strategy comes with its personal distinctive problems, particularly since many SLT methodologies are applied manually.
Take a look at protection challenges
Utilizing typical design for check (DFT) strategies to generate check patterns forward of manufacturing ramp, chip designers are fortunate to get 99% protection of all of the transistors. Nonetheless, for gadgets with 100 billion transistors, similar to in the present day’s superior synthetic intelligence (AI) processors, 1 billion transistors nonetheless go untested. Utilizing purely ATE check strategies, attaining that final 1% of check protection might take months of growth and important tester time.
Furthermore, in the present day’s complexity of integrating heterogeneous chiplets into one giant package deal challenges the soundness and repeatability of the electromechanical stack-up in a high-volume check setting. There are restricted check entry factors to the skin world that should stimulate pathways by means of a number of dies.
As a result of the packages are giant, there could also be warpage and restricted mechanical compression factors for actuating the device-under-test (DUT) connections within the socket. Exercising processors and recollections inside the identical package deal underneath excessive check circumstances, there are inevitable scorching spots that should be managed to forestall injury to the gadget.
To supply a sturdy automated system-level tester with excessive availability in manufacturing, the client check content material should be tightly built-in with socket actuation and thermal management, together with energy administration and check sequencing.
Compounding the complexity of check content material growth is what number of events could also be concerned in optimizing the SLT insertion. Distributors of SLT tools, sockets, and design and check IP should collaborate with the silicon designer/integrator, customized ASIC end-user, outsourced semiconductor meeting and check suppliers (OSATs), board designers, and even prospects—for instance, producers of information facilities, pc distributors and cellphone gadgets—to verify the check station represents the real-world utility it’s supposed to check.
Because the demand for processing energy will increase, chip designs have developed to satisfy market necessities. This improve in processing energy ends in larger power consumption and warmth technology. So, check time for a typical SLT insertion generally is a half hour or extra, requiring many check stations to satisfy the month-to-month quantity calls for.
The buildings constructed to check the components should have particular amenities for electrical energy and thermal management. Subsequently, these check amenities intention to maximise their funding by testing as many gadgets within the smallest ground area as attainable. Nonetheless, the gadgets and their check utility boards are getting larger and devour extra energy.
Rising developments in chip testing
Chip designers and EDA distributors have developed and launched new DFT strategies that permit structural check content material to be delivered as packetized knowledge over normal high-speed serial ports like USB and PCIe. Throughout SLT, these ports should be enumerated on the utility stage in order that the port operates as supposed.
As soon as this connection is made, the check program can swap right into a check mode utilizing a small variety of high-speed pins to run structural check patterns or different built-in self-test features. As soon as these serial knowledge ports are working, the check content material could be reused and correlated both to ATE with comparable check stations (similar to Hyperlink Scale) or post-silicon validation check stations (similar to SiConic) to enhance time to market and reuse.
Managing the warmth dissipation of those high-power gadgets underneath excessive workload is a ubiquitous downside being addressed on the engineering, bench, ATE and SLT check insertions, and even in data-center-wide operation. Air, liquid, and refrigerants are all utilized, with a watch on environmental sustainability. Manufacturing check handlers have the added problem of biking warmth and mechanical engagement a number of occasions per day.
The usage of AI and machine studying (ML) can be being utilized to semiconductor testing. Sharing the check end result knowledge between completely different check insertions, together with ATE, burn-in, and SLT, feeds into AI and ML instruments to enhance yield, speed up test-program growth, and optimize check occasions.
Wanting forward
As semiconductor manufacturing turns into extra advanced, SLT will proceed to develop in significance. For it to be actually efficient, firms should combine it into their general testing technique relatively than treating it as a separate, remoted step. And the subsequent technology of system-level testers should concentrate on addressing the challenges cited above. Success would require collaboration throughout design, check, and high-volume manufacturing groups, in addition to a willingness to rethink conventional approaches to validation.
In an period outlined by multi-chip packages, heterogeneous integration, and ever-tightening efficiency calls for, SLT will stay a vital device for making certain that cutting-edge chips carry out as anticipated in real-world functions.
Davette Berry is senior director of Buyer Applications & Enterprise Growth at Advantest.
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