The SKY63104/5/6 household of jitter-attenuating clocks and the SKY62101 clock generator concurrently generate ultra-low jitter clocks for synchronous Ethernet and spread-spectrum PCIe. Constructed on Skyworks’ fifth-generation DSPLL and MultiSynth applied sciences, these units assist versatile input-to-output frequency mapping and allow single-IC clock tree designs for demanding networking, knowledge middle, and industrial purposes.
Typical DSPLL RMS jitter is as little as 18 fs (12 kHz–20 MHz at 625 MHz), with complete output jitter round 55 fs RMS—effectively fitted to 224G PAM4 Ethernet SerDes. The units additionally meet unfold spectrum clocking necessities for PCIe Gen 1 via Gen 6.
The jitter attenuators and clock generator present 12 outputs in a compact 8×8-mm QFN bundle with wettable flanks. The SKY63104 consists of one DSPLL with two MultiSynths; the SKY63105 has two DSPLLs and one MultiSynth; and the SKY63106 options three DSPLLs with no MultiSynth. Output frequencies span 8 kHz to three.2 GHz, with configurable codecs together with LVDS, HCSL, LVPECL, LVCMOS, S-LVDS, and CML. Output-to-output skew is tightly managed at ±50 ps, with per-output delay adjustable in 50-ps steps.
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