Location: Pune
Firm: Cadence
Obligations
- Design Verification for interconnect IP
- Related expertise in interconnect and subsystems is strongly most popular
- Crafting verification plans and executing on these plans to confirm extremely complicated and configurable designs.
- Answerable for protection assortment and closure
- Work carefully with cross purposeful groups (DV/Arch/Design/FW) to determine protection scope
Required Expertise and Expertise
- 2+ years of design verification expertise
- BS/MS (or greater) in EE/Pc Engineering
- Sturdy technical and interpersonal abilities
- Glorious information of Interconnects, NoCs and design verification fundamentals.
- Thorough understanding of System Verilog, UVM, and different programming languages to construct versatile and reusable complicated testbenches
- Expertise with growth of absolutely automated flows
- Publicity to scripting languages like Perl, Unix shell or related languages
- Expertise with Formal Verification might be a plus
- Expertise with Gate Stage Simulations
- Glorious written and oral communication abilities vital
