Semiconductor gadgets repeatedly expertise developments resulting in expertise and innovation leaps, reminiscent of we see right now for purposes in AI high-performance computing for information facilities, edge AI gadgets, electrical automobiles, autonomous driving, cell phones, and others. Current expertise improvements embrace Angstrom-scale semiconductor processing nodes, high-bandwidth reminiscence, superior 2.5D/3D heterogeneous built-in packages, chiplets, and die-to-die-interconnects to call a couple of. As well as, silicon photonics in a co-packaged optics (CPO) kind issue guarantees to be a key enabling expertise within the subject of high-speed information communications for high-performance computing purposes.
What’s CPO?
CPO is a packaging innovation that integrates silicon photonics chips with information middle switches or GPU computing gadgets onto a single substrate (see Determine 1). It addresses the rising demand for interconnects with larger bandwidth and velocity, low latency, decrease energy consumption, and improved effectivity in information switch for AI information middle purposes.
Determine 1 Co-packaged Optics (Supply: Broadcom)
To grasp CPO we have to first perceive its constituent applied sciences. One such important expertise for CPO is silicon photonics. Silicon photonics supplies the foundational expertise for integrating high-speed optical features immediately into silicon chips. CMOS foundries have developed superior processes based mostly on silicon semiconductor expertise to allow photonic performance on silicon wafers. CPO makes use of heterogeneous built-in packaging (HIP) that integrates these silicon photonics chips immediately with digital chips, reminiscent of AI accelerator chips or a swap ASIC, on a single substrate or package deal. Collectively, silicon photonics and HIP ship CPO merchandise. Thus, CPO is the convergence of silicon photonics, ASICs and superior heterogeneous packaging functionality provide chains.
As talked about earlier, CPO brings high-speed, excessive bandwidth, low latency, low-power photonic interconnects to the computation beachfront. As well as, photonics gadgets are virtually loss-less for big distances enabling one such AI accelerator to share workloads with one other AI accelerator a whole bunch of meters away, whereas appearing as one compute useful resource. This high-speed and long-distance interconnect CPO cloth guarantees to re-architect the information middle, a key innovation to unlock future AI purposes.
Early CPO prototypes are being developed as of 2025 which combine photonics “engines” with the swap or GPU ASICs on a single substrate, quite than utilizing superior heterogeneous packages for integration. The optical “engine” on this context refers back to the packaging of the silicon photonics chips with different discrete parts plus the optical fiber connector; and CPO on this context refers back to the meeting of a number of optical engines with the swap or GPU ASICs on a standard substrate.
Learn how to Shorten CPO Time to Market?
The datacom marketplace for CPO presents a possibility measurement of about two orders of magnitude larger than what silicon photonics manufacturing provide chains have been traditionally accustomed to dealing with, such because the high-mix, low-volume merchandise and purposes in telecom and biotech. To efficiently obtain CPO at this larger quantity, three components must advance:
- The silicon photonics provide chain must scale up capability and obtain excessive yields at wafer and on the optical engine stage.
- New heterogeneous built-in packaging ideas have to be confirmed with the OSATs and contract producers for co-packaged optics.
- New, high-volume check methods have to be developed and confirmed, as the present silicon photonics testing processes are extremely handbook and never scalable for prime quantity manufacturing.
CPO expertise just isn’t mature or at excessive quantity but, however check tools suppliers and machine suppliers have to be prepared for its arrival because it has a direct influence on automated check tools check necessities, whether or not on the wafer, package deal, or system stage. Investments in photonics testing capabilities are important for creating hybrid testing techniques that may preserve tempo with fast developments in photonics, and may deal with each electrical and optical alerts concurrently. CPO testing requires energetic thermal administration, excessive energy, massive package deal dealing with, customized photonic dealing with and alignment, high-speed digital signaling, wide-band photonic signaling, and excessive frequency RF sign testing.
Moreover, there are a number of check insertions from wafer to last package deal check that have to be optimized for check protection, check time, and price (see Determine 2). Experience and expertise are required to optimize the check protection at every insertion to keep away from incurring important product manufacturing price in each operational expense and capital tools.
Determine 2: Silicon Photonics Wafer-to-CPO Check Insertions
CPO Check Challenges
Testing CPO gadgets presents distinctive challenges as a result of numerous processes and supplies concerned, each electrical and photonics. A novel problem lies within the inherent complexity of aligning optical parts with the precision wanted to make sure dependable check outcomes. Optical alerts are extremely delicate to minute deviations in alignment, in contrast to conventional electrical alerts, the place connection tolerances are extra forgiving. The intricacies of CPO, which combine photonics with high-digital content material computing gadgets, demand exact positioning of lasers, waveguides, and photodetectors. Even the smallest misalignment may end up in sign degradation, energy loss, or inaccurate measurements, complicating check processes. As this expertise advances, automated check tools must evolve to accommodate the exact necessities posed by photonics and optical-electrical integration.
Along with the precision required, the supplies and processes concerned in CPO introduce variability. When a number of optical chiplets from totally different suppliers, every utilizing probably totally different supplies or designs, are packaged right into a single substrate, sustaining alignment throughout these disparate components turns into exponentially harder. Every optical chiplet might have its personal distinctive optical properties, which means that check tools should deal with a variety of optical alignments with out compromising the accuracy of sign transmission or reception. This will increase the demand for automated check tools to adapt and supply constantly dependable measurements throughout varied forms of supplies and optical designs.
The time-consuming nature of attaining exact alignment additionally creates a major bottleneck in high-volume semiconductor testing environments. Aligning optical parts, usually manually or by way of semi-automated processes, provides time to check cycles, which might negatively influence throughput and effectivity in manufacturing environments. To mitigate these delays, automated check tools suppliers should put money into superior photonics testing capabilities, reminiscent of hybrid techniques that may deal with each electrical and optical alerts concurrently and effectively. These techniques should additionally incorporate quicker, extra dependable alignment methods, probably leveraging AI-driven calibration and adaptive algorithms that may regulate in real-time.
Check meets the high-stakes wants of CPO
With the push for quicker information interconnects supporting the most recent business protocols—reminiscent of PCIe 5.0/6.0/7.0 and 400G/800G/1.6T b/s Ethernet, and past—the stakes are excessive for information middle reliability and efficiency. Any failure or suboptimal efficiency in information interconnects can result in important downtimes and efficiency bottlenecks. Consequently, there’s a larger emphasis on enhanced check protection to establish and handle potential points earlier than the parts are deployed in information facilities. In consequence, the semiconductor check business should present complete check options that cowl all facets of element efficiency, together with sign integrity, thermal conduct, and energy consumption beneath a variety of working situations.
In the end, the business’s shift towards CPO will demand a change in check methodologies and tools, with particular emphasis on correct optical alignment in any respect check insertions, from wafer to CPO packages. Semiconductor check leaders who put money into superior photonics testing techniques can be higher positioned to deal with the complexities of this rising expertise, guaranteeing that they will preserve tempo with each fast developments and rising market calls for.
Teradyne is on the forefront of those improvements anticipating new applied sciences and taking a proactive method to creating versatile and efficient automated check tools capabilities for the most recent developments in semiconductor packaging and supplies.
Dr. Jeorge S. Hurtarte
Senior Director, SoC Product Technique Semiconductor Check group
Teradyne
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