Navitas Semiconductor’s newest GeneSiC MOSFETs exceed AEC-Q101 requirements, extending lifetime in automotive and industrial programs. Based mostly on trench-assisted planar expertise, they’re obtainable in HV-T2Pak top-side cooled packages with 6.45-mm creepage and a CTI above 600 V, supporting IEC-compliant operation as much as 1200 V.
Navitas makes use of the time period AEC-Plus to designate elements that exceed the AEC-Q101 reliability exams revealed by the Automotive Electronics Council (AEC), based mostly on multi-lot stress-test outcomes. This in-house benchmark layers extra stress situations onto commonplace AEC-Q101 and JEDEC protocols to raised mirror real-world automotive and industrial mission profiles by:
- Incorporating dynamic reverse bias (D-HTRB) and dynamic gate switching (D-HTGB) exams
- Operating power- and temperature-cycling for over twice the usual length
- Extending static high-temperature, high-voltage exams (HTRB, HTGB) to over thrice the AEC-Q101 interval
- Qualifying elements to 200 °C TJMAX for improved overload functionality
Housed within the 14×18.5-mm HV-T2Pak, the preliminary portfolio consists of 1200-V gadgets with on-resistance from 18 mΩ to 135 mΩ and 650-V gadgets starting from 20 mΩ to 55 mΩ. Decrease on-resistance (<15 mΩ) SiC MOSFETs in the identical package deal will comply with later in 2025. For extra info on GeneSiC MOSFETs, click on right here.
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