The EDA trio—Cadence, Siemens EDA, and Synopsys—was distinguished on the Intel Foundry Direct Join 2025 whereas lining up AI-driven analog and digital design flows for Intel’s 18A course of node. The choices additionally included IPs starting from SerDes to DDR5 to Common Chiplet Interconnect Categorical (UCIe).
Subsequent, these EDA outfits inked superior packaging partnerships by providing workflows for Intel Foundry’s Embedded Multi-die Interconnect Bridge-T (EMIB-T) expertise, which mixes the advantages of EMIB 2.5D and Foveros 3D packaging applied sciences for prime interconnect densities at die sizes past the reticle restrict.
Let’s begin with EDA flows.
Cadence has licensed its RTL-to-GDS movement for 18A course of design package (PDK), which incorporates the Cerebrus Clever Chip Explorer, Genus Synthesis answer, Innovus Implementation System, Quantus Extraction answer, Quantus Area Solver, Tempus Timing answer, and Pegasus Verification System.
Siemens EDA has licensed its Calibre nmPlatform sign-off instrument and Solido SPICE and Analog FastSPICE (AFS) software program instruments for 18A manufacturing PDK. Likewise, the qualification of Calibre nmPlatform and Solido Simulation Suite choices for the Intel 18A-P course of node is now underway. These EDA instruments are additionally a part of the Intel 14A-E course of definition and early runsets already obtainable.
Determine 1 Synopsys unveiled an EDA and IP collaboration roadmap with Intel Foundry on the occasion.
IP and superior packaging liaison
Cadence has introduced a broad vary of IPs for the 18A course of node. That features 112G prolonged long-reach SerDes, 64G MP PHY for PCIe 6.0, CXL 3.0, and 56G Ethernet, LPDDR5X/5 – 8533 Mbps with multi-standard help, and UCIe 1.0 16G for superior packaging.
Apart from IP choices, Cadence is partnering with Intel Foundry to develop a complicated packaging workflow to leverage EMIB-T expertise. This workflow will streamline the combination of advanced multi-chiplet architectures whereas complying with requirements.
Determine 2 Cadence is certifying EDA toolsets and IPs for Intel’s 18A course of node.
In the meantime, Siemens EDA has introduced the certification of a reference workflow for EMIB-T expertise utilizing via silicon by way of (TSV) approach. It’s pushed by the corporate’s Innovator3D IC answer, which supplies a consolidated cockpit for developing a digital twin. It additionally incorporates a unified knowledge mannequin for design planning, prototyping, and predictive evaluation of full bundle meeting.
Synopsys can be using its 3DIC Compiler to facilitate a reference workflow that allows environment friendly EMIB-T designs with early bump and TSV planning and optimization. It additionally options automated UCIe and HBM routing for prime quality of outcomes and quick 3D heterogeneous integration. Right here, the 3DIC Compiler facilitates feasibility and partitioning, prototyping and floorplanning, and multiphysics signoff in a single surroundings.
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